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RE: [802.3af] quick questions

See my comments below.

> -----Original Message-----
> From:	Dave Dwelley [SMTP:ddwelley@xxxxxxxxxx]
> Sent:	ε, ιεπι 22, 2001 8:58 PM
> To:	Yair Darshan; Yair Darshan
> Cc:	'stds-802-3-pwrviamdi@xxxxxxxx'
> Subject:	RE: [802.3af] quick questions
> Yair -
> More comments on the inrush issue:
> At 05:10 AM 6/16/2001 +0200, Yair Darshan wrote:
> >         In type A, the isolating switch is working as a simple switch
> which
> >turn on at around 32V with out hesterhisis.
> >         The switch is turn on within few mSec. The switch is turn on by
> >passing through the switch (Mosfet) linear region, which represents a
> >resistor of 50-100 ohms.
> >         It means that it limits the current to a value that is greater
> than
> >0.5A (more close to 1A) and since the PSE inrush current limit is set to
> >0.5A, this effect in the PD is not relevant.
> >         The PD power supply controller contains UVLO that is set to turn
> on
> >at around 40V and turn of at around 33V. it is located after the big
> >cap(part of PWM controller)
> Correct me if I'm wrong, but doesn't this type A circuit effectively split
> the dissipation between the PSE current limit FET and the PD UVLO FET? It 
> will regulate the line voltage at turn-on to the UVLO level, and the rest 
> of the dissipation will be in the PD. This means the PD switch needs to 
> consider power dissipation as well as the PSE switch - it's not
> necessarily 
> a tiny FET any more.
	[Yair Darshan]
	1. If the inrush current in the PSE is set to 0.5A , the isolating
switch (type A) does not function as current limit since it inherent ability
to limit the current is much higher than 0.5A. 
	2. In type A circuit we have two basic isolating switch scheme. Lets
defined them as scheme a and scheme b. scheme a  contains one Mosfet and 2
resistors performing the signature resistor and setting the threshold
voltage of the switch. In this scheme it does split the power dissipation
between PSE switch and isolating switch in the PD. In this case the power
dissipation across the switch is function of the PD input cap size and the
time required to the isolating Mosfet gate to reach its threshold value for
on condition.
	In scheme B, the isolating switch is design to switch much faster
and the power dissipation is 10 times lower than scheme a.
	It contains few more components to and during startup you have the
port voltage across the PD input for few msec (can be set to any number) and
it goes to zero and start ramping until reaching Vport. 

	Bottom line is that the isolating switch can be implemented and
several ways, few of them are with very low power dissipation allowing the
use of small Mosfet package. 

	Please not that if you want to use this circuit as inrush current
limit, you can do it however you need much more components to implement this
function for the extent
	required to answer the following requirement:
	1.  Filtering transients in the current.
	2.  Performing accurate current limit if it is set to the max.
available current in order to utilize all power available.
	     If you want to set it to much lower current than the max., you
need to change the threshold at normal operating mode.
	3.  You need reset circuit to allow inrush current function if the
PD is disconnected in reconnected again within TBD ms.
	4.  You need sense resistor etc.

	All this functions and components you will have it in the PSE

> Type B is obviously OK since it has no isolating switch. We can't use it 
> because it won't allow detection.
	[Yair Darshan]  Yes I agree with you. I have mention it to
demonstrate the level of confidence of a system that have inrush current
limit in the PSE and nothing in the PD and yet we don't have inter-operate
problems or other since it is truly simple.
	And the addition of isolating switch to allow resistor detection
doesn't change anything.

> I'm most worried about a "type C", with a hysteretic turn-on in the PD. 
> This scheme minimizes dissipation in the PD, allowing the smallest 
> isolation FET. It can also oscillate at turn on with a current-limited
> PSE.
	[Yair Darshan]  Why you worried about it isn't it a matter of well
defined spec and the art of comply to this spec?
	From the tests that we have run, we didn't had this oscillations. I
agree that it could be however , it could be even if you have inrush current
limit in the PD if the designer didn't design for meeting the voltage
levels, current levels and timing required. 

> The isolating switch is the big headache here, since it's highly 
> non-linear. Even type A can oscillate at startup if conditions are wrong -
	[Yair Darshan]  It is true always regarding of where the inrush is
located as I have mentioned above.

> it is a common source amplifier with gain and phase shift (and a
> capacitive 
> load!), and the PSE current-limited output also has loop behavior. 
	[Yair Darshan]  The isolating switch scheme a and scheme b are 1st
order system during transition hence unconditionally stable. Stability can
be increased by adding 
	small cap to the mosfet gate source.
	The PSE current limit is also a stable circuit ( designed to be
single pole system, with large phase and gain margins).
	Dave: Stabilizing the closed loop of the DC/DC switching regulator
in the PD or in the PSE is an order of magnitude complicated than
stabilizing current limit with capacitive load and yet it works.

	I can send you the spice source models to play with it in order to
feel how simple it is. 

> Today's 
> circuits don't oscillate, but as FET/IC technology advances, other 
> solutions will become cost effective - and they may oscillate.
	[Yair Darshan]  Again it is a matter of implementation and not a
conceptual problem. Any circuit can oscillate if it hasn't designed

>  We haven't 
> even entered the realm of power supply behavior yet - the PD supply is 
> still in UVLO, and the large PSE supply is well below its current limit. 
> The oscillator is composed of the PSE inrush (outrush?) limiter and the 
> isolation switch circuit in the PD.
	[Yair Darshan]  Dave, the description above is theoretical potential
problem which practically it is not a problem any more. It is working.
Nothing special about it.
	See system model from March 2001 presentation. It is real system and
its work with large margin. 

> I like the PD-inrush circuit because all of the possible oscillating 
> elements are in the same box (the phone), and all are supplied by the same
> vendor. If the vendor does his job right, the phone won't oscillate.
	[Yair Darshan] 
	What ensures that the chips in the PD supplied by vendor A will work
fine with the hardware of vendor b within this PD?
	The answer is that the designer is working according the spec of
vendor a to interface with his hardware (vendor b)
	Now the definitions of vendor a are located in the PSE. Isn't it the
same case? 

	Now imagine that the above vendor doesn't need to add inrush current
limiting function and he is connected to a source that equipped with this
	If he is testing his PD by connecting to A supply that has inrush
current limiting specified to TBD A and TBD ms and he is not oscillating,
than he is O.K.
	Since all the PSE's will comply the TBD A and TBD  msec. The gain is
less components in the PD.

>  If he 
> screws it up and it oscillates, he's a bad PD designer - don't buy his 
> phones. The PSE current limit circuit is open loop during power-up, so it 
> can't contribute. Even if we have a bad phone that oscillates internally, 
> the voltage on the wire won't oscillate, and data disturbance is
> minimized.
	[Yair Darshan]  See above.

> In the PSE-inrush case, half of the loop (the PSE current limit) is made
> by 
> one vendor, and half of the loop (the PD iso switch) is made by another. 
	[Yair Darshan]  The same is with the power supply. PSE power supply
is done by vendor A and PD power supply is done by vendor B and yet they
both required to work together without stability problem and they will if
they are designed to comply with the same spec.
> No
> vendor can test his PSE against future PD designs, nor can a PD designer 
> test against future PSEs. Unless we specify impedances, phase margin, 
> frequency bands, etc.,
	[Yair Darshan]  I agree.
>  we can't guarantee it won't oscillate with some 
> future yet-to-be-designed PD, and a PD designer wishing to test his phone 
> can't be sure he won't oscillate unless he buys every PSE available...
> I'm guessing that this cross-brand interoperability issue hasn't really 
> been tested in the field, since most current systems (that I'm aware of) 
> are proprietary and only work with their own phones. True?
	[Yair Darshan]  No. There are one for sure and maybe two systems in
the market that the PSE was tested with many different PD vendors.
	We don't know of a PD tested with many PSE's.

> > > Your 350uF number is fine for dissipation at turn-on, and it's
> marginal
> > > but
> > > probably OK (57V*400mA*50ms=1.14J)
> >         [Yair Darshan]  I think you have mistake here. The calculation
> is
> >57*400mA*50mSec/2 = 0.504Joul. So you have 100% margin. You need to
> divide
> >by 2 since it is triangle shape for a constant current charging a cap.
> >Please check me again.
> For power up, you are correct. For a shorted line, there is no triangle 
> waveform, and the /2 factor disappears - although thermal limit will still
> save us.
	[Yair Darshan]  Yes I am counting on thermal protection or other
methods to differentiate between the two cases.
	I don't see a problem here, we have tested both cases. When you have
complete short and when you are ramping up.
	There are already thermal protection solution in the market that
works fine.
	Other method is to measure the voltage across the switch and the
current and make a logical decision. 

> Like you say, the PSE inrush solution works in the field today. I believe 
> this is true. I fear it won't always be - and I'll sleep better if we 
> mandate PD inrush control. We agreed in St. Louis to accept up to TBD cap 
> without PD inrush, and I'm prepared to supply chips that will work 
> thermally with 350uF. But I can't guarantee they won't oscillate!
	[Yair Darshan]  If you will design your chip according to a given
spec. and test your chip by loading it with a TBD setup that we can define
together, the chance for having oscillation will be almost zero. 


> Dave