Candidate Detection Tolerance Allocation and Test Limits
Folks,
At my request, David Law has posted slides that attempt to tune up the
tolerance allocation limits presented at the Nov IEEE meeting. Please see,
http://www.ieee802.org/3/af/public/documents/tolerance-tune-up-A.pdf
Those slides give three scenarios. The only difference is the slope
calculation precision assumed for the PSE (+/- 3%, +/- 5%, +/- 8%).
The intent is to help move us to agreement on a slope determination
precision level that is practical for analog devices (no micro controller),
while still accepting a fairly
compact part of V-I space.
**** I particularly invite input from silicon house representatives (as
well as others), on the feasibility/acceptability of these three cases. I
would lean toward keeping to +/- 5% or lower, but we need discussion.
The basic allocation philosophy is to keep tolerance tight on the PD and to
allow the PSE to
accept a wider area to ensure power delivery. Keeping PD tolerance tight
also facilitates having less precision in PSE slope determination, and
preserves
space for multiple power classes IF that is adopted.
I think it would be good to keep the final budget in an appendix of the
standard to show how we got to where we did.
The accept/reject template concept is consistent with what we discussed in
Tampa and similar to Rick Brooks' recent templates. These slides
concentrate on "what numbers" and why.
--
Donald (Don) S. Stewart Phone: 732-817-5495, FAX x4666
Avaya Inc. e-mail: dsstewart@avaya.com
Cross-Product Architecture
101 Crawfords Corner Road
Holmdel, NJ 07733