Memory channel (MC) working group:

The memory channel (MC) study group was authorized by the IEEE MSC at their 2004Jan12 meeting.
This study group generated a project authorization request (PAR) that was approved by the IEEE. Questions should be directed to the MSC Chair or the Study Group Chair.

The scope of this project is to develop a flexible, scalable, secure data interface to transfer data to and from storage. This protocol will be technology independent, to be supported by current communications links, and will remove size and distance limitations on data retrieval, with additional data redundancy and data coherency methods.

This project will develop a memory transport protocol capable of supporting data growth and data security requirements in the changing microprocesor environment. Memory is stored data in many forms and locations. This Memory Channel protocol shall be independent of link technology. This protocol shall be capable of transparent, secure, access to large, local and remote memory systems, employing coherent and redundant storage methods.

The reason for developing this Memory Channel Standard is to remove the limitations on size, distance, shape, speed, and security levels associated with the access to stored data devices - memory - including RAM, ROM, flash, disk, and any other method(s) of storing information. This Memory Channel Standard will be a generic memory interconnect that:

1. Removes any memory size and location constraints.
2. Is an extensible design with room for options and future developments.
3. Defines a memory channel protocol indepentent of any link technology.
4. Does not change at each new processor design.
5. Will be capable of plug-n-play operation.
6. Capable of redundant arrays of inexpensive memory modules (RAIMM) operation (RAID with/without rotation).
7. Design optimized for flexability and versitility over performance.
8. Provide extensive data protection in addition to link level protection.
9. Provide for data security required- assume all transactions monitored.
10. Supports smart memory modules concepts.
11. Supports remote direct memory access (RDMA).

The beneficiaries of Memory Channel Standard are:

1. Processor vendors-No needed knowledge of memory module architecture.
2. Memory vendors-More optimized memory design, less physical driving contraints-Add interface to chip for smallest systems.
3. System builders-More options for memory, better signal integrity design, faster time to market, capable of upgrade after sale, expanded system architecture to meet specific design goals, component compatibility over time for longer product life.
4. Memory module vendors - More design freedom in sub-unit design, opportunity to add capabilities for differentiation, memory is memory is memory - different technologies.
5. Users - plug-n-play, capable of upgrading system memory and performance, ability to support special applications needs, expanded memory solutions available with wider cost/performance options.

• Click here to join the reflector
• Meeting schedule (TBD, possibly late October, 2004)
• Minutes:
• Contributions:
• Preliminary proposal