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Another missing feature in VHDL


I started working on our very old list of interfaces we collected, to check them with a vendor tool supporting interfaces (views) before I propose an open source release.

Take for example the I²C interface.
Some more official naming uses SCL and SDA, because it's used in IC datasheets and schematic designers are mainly non-programmers. They like short unreadable names in overfilled schematics.

On the other hand, we are ASIC or FPGA designers who write (hopefully) clean code. We would like to use a more descriptive name like SerialClock, SerialData. Or maybe, it's obvious that I²C is serial, so just Clock and Data.

My point is, we can't implement all different naming styles or ideas with VHDL interfaces, because it's based on records and each record type definition gives us an individual type. With Ryan's addition of closely related composites, we could convert two I²C naming variants.

-- signal fpga_signal : T_I2C_FPGA;
-- signal pcb_signal  : T_I2C_PCB;

fpga_signal <= (T_I2C_FPGA) pcb_signal;

BUT, this only works for records with all subelements with the same mode (same direction).

While this seems simple or overkill for an I²C interface, other interfaces like AXI are more complex.
1. one record for all signals with original unreadable names from ARM
2. 5 records in a top-record, one record per stream
3. full decomposition, so no repeated code/definitions

In VHDL, we can handle some of these problems with aliases.

What we currently can't do, is a "composite alias" or "record alias".
(I have currently no good name for it.)

-- long names
type T_I2C_FPGA is record
  SerialClock : std_logic;
  SerialData  : std_logic;
end record;  

-- naming like in most datasheets
type T_I2C_PCB is alias record
  SCL is T_I2C_FPGA.SerialClock;
  SDA is T_I2C_FPGA.SerialData;
end record;

Ideally, we could use a simple assignment:
fpga_signal <= pcb_signal;

In a more explicit way, we could use a conversion to apply this alias record
fpga_signal <= (T_I2C_FPGA) pcb_signal;  

Other use cases are:
* UART: RX,TX versus RxD, TxD

This idea is not about mapping interfaces of different sizes or amount of subelements. It's just naming.

Of course, you can also propose alternative ideas to solve the problem from above.

Kind regards

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