ECID - Electronic Chip ID

1149.1-2013 defines a new, optional instruction called ECIDCODE, a Test Data Regiser called ECID and a new procedure "ecid" for the IC manufacturer or IP provider to document how to read the unqiue ID from a die compliant with the standard. The ECID register should not be confused with the more restricted DEVICE_ID register. The ECID register is unique per die and may include Wafer X-Y locations, lot information, wafer number, binning information for temperature and speed grade and any other information deemed appropriate for traceability.

While ICs have traditionally been tested standalone in an almost ‘noise-free’ ATE environment and/or tested with limited structural tests to see whether they perform to their specifications, the board/system environment can be quite different in terms of noise, timing margin, voltage and functional test trigger conditions that structural tests were unable to reproduce.  Board yield and IC DPM can be improved significantly when traceability from board level back to the wafer is possible. Board/system level failures can drive enhanced screening back at the IC suppliers test or minimal IC level tests can drive increased test coverage at the board or system.
The four types of Adaptive Test (In-situ, Feed-forward, Feed-back and Post-test) can all be extended to be used during board and system manufacturing. Some examples of adaptive test methods for board and system include:

One of difficulties to extend the chip-level adaptive test to board/system or even in-field test is to track their test trigger conditions and be able to convert between them. For example, chip-level scan-based logic gate test may not be always applicable for board/system/in-field tests due to the difficulties or impossibilities to control the scan chain data, clock pulse, non-stoppable in-field online function executions, etc.   

Similarly, a functional execution, which can be treated as a functional test may be hard to convert to a chip level ATE test because the function execution could involve memory contents, their transactions, logic and I/O data flow, etc. Therefore, tracking the test/failure conditions and the capability to convert between them is the key for adaptive test extension to board/system level.

IEEE 1149.1-2013 provides guidance here; the new standard enhances 1149.1 for Adaptive Test by standardizing infrastructure needed for tracking and in-situ board level test of an IC. Tracking is performed by the standardization of the Electronic Chip ID in the standard.   In-situ board level test of an IC is supported by the 1149.1 standardization of IC reset control necessary for internal IC initialization (via IC_RESET instruction) and I/O isolation (via CLAMP_HOLD) such that the I/O are isolated from noise and system level activity while IC level test patterns are applied.  The architecture is such as to mitigate false failures which would exacerbate the problem of good data collection for Adaptive Test.

While all the examples are useful and feasible, they require extensive data infrastructure, analysis, exchange and security. Companies providing ICs, board design and test need to openly collaborate on a technical and business level to be successful.

ECID retreival description in 1149.1-2013 PDL