From: owner-stds-1149-4wg To: stds.1149.4wg Subject: Last minute mail... Date: Friday, October 20, 1995 11:09AM Hello .4, Undoubtedly this mail arrives too late for many of you to print it out before the .4 meeting, so I'll bring copies. -kp- ----------- Hello Adam, I have received zero feedback on some observations I made in D05 that were addressed to the WG. Perhaps they were buried too deep for all to see. In particular I'd like your opinion of whether the WG should take a few ;-) minutes to discuss instruction modes. I think we can become coherent on this (finally) if we give it a try. I'll reproduce my recommendations below. ------- Forwarded Message In figure 10, I worked out the logic equations for the switches; first label the 3 update latches X, Y and Z left to right. Lable Mode M. Then: S1 = M* (the * shows inversion) S2 = MX*Y S3 = MXY S4 = XY* S5 = Z Now S2 switches +V and S3 switches G, so the two together can be thought of as a pseudo-dot-1 driver with X being the dot-1 data cell and Y being the dot-1 3-state control cell, EXCEPT, the inversion of X should be moved from S2 to S3. Otherwise, existing Dot-1 software cannot create interconnect tests for pseudo-dot-1 testing in Dot-4 ICs. Change S2 to MXY and S3 to MX*Y and we can use today's software unchanged! -------- In figure 10, the lines marked AT1 and AT2 should be AB1 and AB2. ------------------------------------------------------------------------ Now consider some inconsistancies; we say in several places (typically when discussing BYPASS and SAMPLE) that the core circuitry is unhindered by the test logic when these instructions are in effect. In Dot-1, this is enforced by the Mode line coming from the TAP. See the classic Dot-1 Boundary Register cell below: Mode>------------+ | v ______ Core>-----------+----------------------------------|1 | | SO | | | ^ | |----> Pin | _____ ______ | ______ | | +--|1 | +--|D Q|--+--|D Q|------|0 | | | | | | | | ------ | |-+ | Cap| | Upd| | | | | | | +--|0 | +--|> | +--|> | | ----- | ------ | ------ | ^ | | | | | | | | | | SI | | Update_Clk Shift | Capture_Clk For BYPASS and SAMPLE, Mode is 1 and for EXTEST, Mode is 0. This Boundary cell always uses Mode to select between the Core and the Update latch. In P1149.4, this is no longer true in Figure 10. Only three switches, S1, S2 and S3 are controlled by Mode, leaving S4 and S5 to be controlled solely by values stored in the Boundary Register. Thus during BYPASS and SAMPLE, it is possible to have the AB busses connected to pins. This is NOT mission mode and illustrates that we do not yet have a definition of instruction modes. Discussion for the full WG: We need to define just what we mean by SAMPLE, BYPASS, EXTEST and others. Since we are riding on Dot-1 coattails, we should strive to have identical meanings for terms. Lets take them one by one. BYPASS: Places 1 bit bypass register in TDI/TDO path. Contents of all registers have NO EFFECT on core functionality, meaning in particular that no +V, G, AB1, AB2 switches are closed; that AT bus is not connected to AB bus; and AB lines are shunted to the safe DC voltage. SAMPLE: (Also known by PRELOAD) Places Boundary Register in TDI/TDO path for shifting. At the Capture-DR state, the capture FFs capture data as per the 1149.1 rules for digital cells. In analog boundary modules, the "X" FF captures the digitized value of the pin. The "Y" and "Z" FFs could capture anything, but capturing their Update FF state would improve module testability. Otherwise, core operation is completely unhindered by the test logic, as in BYPASS. EXTEST: Places Boundary Register in TDI/TDO path for shifting. This instruction disconnects all core functionality from all pins. The pins are now controlled by 1149.1 drivers on digital pins, and by the collection of S2-S5 switches in each analog boundary module. The S2-S5 switches are in turn controlled by the content of their Boundary Registers cells. The AB bus is connected to the AT bus and the DC shunt is disconnected. NOTE: EXTEST on analog pins can conduct a pseudo-dot-1 test for interconnect test purposes, or, can be used to conduct analog measurements on external components. This is entirely under control of the Boundary Register contents. While this is going on, any digital pins are under control of the BReg as well, to cooperate with interconnect tests, or to be held quiescent during analog measurements. NOTE: With BYPASS, SAMPLE and EXTEST defined as above to be consistant with Dot-1, we have not yet provided for "analog sampling", where analog pins are to be monitored or even stimulated by the AB bus. I hesitate to call this ASAMPLE because of the loading/stimulation that can occur, so I'll call it AFUNC for the heck of it. AFUNC: Places Boundary Register in TDI/TDO path for shifting. This instruction retains all core functionality for all pins. All digital pins have their mode lines set to allow core functions to propagate to/from pins. All analog boundary modules have their core functions connected to pins. ABM switches S4 and S5 are allowed to function as their BReg cell contents dictate. (Can anyone say S2 and S3 switches should be allowed/disallowed as well??). The ABM "X" FF captures the digitized state of the analog pin at Capture-DR. The AT bus is connected to the AB bus and the DC shunts are disconnected. NOTE: AFUNC allows a chip's analog pins to be monitored on AB2 and/or stimulated by AB1 while the chip is otherwise operating normally. In practice, only one pin should be connected to AB* at any one time. NOTE: The implementation of EXTEST and AFUNC imply TWO (2) mode lines issuing from the instruction decoder. I'll call them M and F. For Figure 10 the S1-S5 equations become (I've fixed the error noted earlier): S1 = M* (the * shows inversion) S2 = MXY S3 = MX*Y S4 = FXY* S5 = FZ And this table gives instruction decodes for M and F. Instruction A M ------------------------ BYPASS 0 0 SAMPLE 0 0 EXTEST 1 1 AFUNC 1 0 I propose that these four instructions be MANDATORY for P1149.4. --------------------------------------------------------------------- ------- End of Forwarded Message Comments: 1) BSDL can be written TODAY for this structure and today's existing 1149.1 software can generate interconnect tests for this structure. 2) The BSDL "safe" bits for this structure (all 3 will be '0') must be managed as the 1149.1 standard specifies. When not explicitly using a BReg cell during a test, it must be set to 0. 3) In .1 usage the meanings of the X, Y and Z cells should be thought of as: X = Pin data (both drive and receive) Y = tristate enable Z = not used, must be loaded with 0 NOTE! -- When Y = 0 (disable driver) the X cell must also be 0. This info is conveyed by the safe bits. 4) In .4 usage the meanings of the X, Y and Z cells should be thought of as: X = connect AB1 to pin Y = not used, must be loaded with 0 Z = connect AB2 to pin 5) When AFUNC is operating, we can monitor the pin on AB2, OR if the switches are bidirectional, ALSO on AB1. This allows differential measurements or other two-pin measurements without additional analog busses. 6) When AFUNC is operating, we can connect AB1 to a pin and (through the switch impedances) inject signals into operating pins. This can be used for noise simulation, etc.