STIL 1.0 {
  Flow 2011;
  DCLevels 2002;
}
Include "./DEMOPat1.stil.gz";
Spec acSpecs {
  Category cat500MHz {
    tShiftRate { Typ '1/50MHz'; }
    tLC { Typ '1/500MHz'; }
    tClkWidth { Typ 'tLC/2'; }
  }
  Category cat250MHz {
    tShiftRate { Typ '1/50MHz'; }
    tLC { Typ '1/250MHz'; }
    tClkWidth { Typ 'tLC/2'; }
  }
  Category cat166MHz {
    tShiftRate { Typ '1/50MHz'; }
    tLC { Typ '1/166MHz'; }
    tClkWidth { Typ 'tLC/2'; }
  }
}
Selector selACSpeed {
  tShiftRate Typ;
  tLC Typ;
  tClkWidth Typ;
}
Signals {
  Vcc Supply;
  Vcco Supply;
  "Clk0" In;
  "Clk1" In;
  "Clk2" In;
  "ScanEn0" In;
  "PrIn0" In;
  "PrIn1" In;
  "PrIn2" In;
  "PrIn3" In;
  "PrIn4" In;
  "PrIn5" In;
  "PrIn6" In;
  "PrIn7" In;
  "PrOut0" Out;
  "PrOut1" Out;
  "PrOut2" Out;
  "PrOut3" Out;
  "PrOut4" Out;
  "PrOut5" Out;
  "PrOut6" Out;
  "PrOut7" Out;
  "SIn"[0] In { ScanIn; }
  "SIn"[1] In { ScanIn; }
  "SIn"[2] In { ScanIn; }
  "SIn"[3] In { ScanIn; }
  "SOut"[0] Out { ScanOut; }
  "SOut"[1] Out { ScanOut; }
  "SOut"[2] Out { ScanOut; }
  "SOut"[3] Out { ScanOut; }
}
SignalGroups {
  "clocks" ='"Clk0"+"Clk1"+"Clk2"'; // #signals=3
  "_pi" ='"ScanEn0"+"PrIn0"+"PrIn1"+"PrIn2"+"PrIn3"+"PrIn4"+"PrIn5"+"PrIn6"+"PrIn7"'; // #signals=9
  "_po" ='"PrOut0"+"PrOut1"+"PrOut2"+"PrOut3"+"PrOut4"+"PrOut5"+"PrOut6"+"PrOut7"'; // #signals=8
  "_si" ='"SIn"[0]+"SIn"[1]+"SIn"[2]+"SIn"[3]'; // #signals=4
  "_so" ='"SOut"[0]+"SOut"[1]+"SOut"[2]+"SOut"[3]'; // #signals=4
  "_in" ='"clocks"+"_pi"+"_si"'; // #signals=16
  "_out" ='"_po"+"_so"'; // #signals=12
  "_all" ='"_in"+"_out"'; // #signals=28
}
SignalMap DEFAULTPINMAP {
  SiteMap  1 { Layout : A1; }
  Vcc PS0;
  Vcco PS1;
  "Clk0" 0;
  "Clk1" 1;
  "Clk2" 2;
  "ScanEn0" 3;
  "PrIn0" 4;
  "PrIn1" 5;
  "PrIn2" 6;
  "PrIn3" 7;
  "PrIn4" 8;
  "PrIn5" 9;
  "PrIn6" 10;
  "PrIn7" 11;
  "PrOut0" 12;
  "PrOut1" 13;
  "PrOut2" 14;
  "PrOut3" 15;
  "PrOut4" 16;
  "PrOut5" 17;
  "PrOut6" 18;
  "PrOut7" 19;
  "SIn"[0] 20;
  "SIn"[1] 21;
  "SIn"[2] 22;
  "SIn"[3] 23;
  "SOut"[0] 24;
  "SOut"[1] 25;
  "SOut"[2] 26;
  "SOut"[3] 27;
}
Timing SpeedGradeTiming {
  WaveformTable "_default_WFT_" {
    Period 'tShiftRate';
    Waveforms {
      "_all" { 01X { '0ns' D/U/Z; } }
      "_all" { LHT { '0ns' Z; '0.1*tShiftRate' L/H/T; } }
      "clocks" { P { '0.25*tShiftRate' U; '0.5*tShiftRate' D; } }
    }
  }
  WaveformTable "_launch_WFT_" {
    Period 'tShiftRate';
    Waveforms {
      "_all" { 01X { '0ns' D/U/Z; } }
      "_all" { LHT { '0ns' Z; '0.1*tShiftRate' L/H/T; } }
      "clocks" { P { 'tShiftRate-tLC' U; 'tShiftRate-tLC+tClkWidth' D; } }
    }
  }
  WaveformTable "_capture_WFT_" {
    Period 'tShiftRate';
    Waveforms {
      "_all" { 01X { '0ns' D/U/Z; } }
      "_all" { LHT { '0ns' Z; '0.75*tShiftRate' L/H/T; } }
      "clocks" { P { '0ns' U; 'tShiftRate/2' D; } }
    }
  }
}
PatternBurst DEMOPat1_burst {
  PatList {
    DEMOPat1;
  }
}
PatternExec DEMOPat1_exec {
  Timing SpeedGradeTiming;
  PatternBurst DEMOPat1_burst;
}
HardBinDefs {
  Pass {
  }
  Fail {
  }
}
SoftBinDefs {
  Pass {
    Bin pass500MHz { Number 1; Color Green; }
    Bin pass250MHz { Number 2; Color DarkGreen; }
    Bin pass166MHz { Number 3; Color Aqua; }
  }
  Fail {
    Bin failFunc { Number 10; Color Red; }
  }
}
Test testFunc {
  Library testPattern;
  Parameters {
    In PatternExec PatExec = DEMOPat1_exec;
    In sigref_expr sigref = '"_so"+"_po"';
  }
}
Flow MAINFLOW {
  FlowNode test500MHz {
    TestNumber 10;
    Category cat500MHz;
    Selector selACSpeed;
    TestExec testFunc;
    ExitPorts {
      Port PASS CurrentExec.ExecResult==Pass {
        SetBin pass500MHz;
        Return;
      }
      Port FAIL CurrentExec.ExecResult==Fail { Next; }
    }
  }
  FlowNode test250MHz {
    TestNumber 11;
    Category cat250MHz;
    Selector selACSpeed;
    TestExec testFunc;
    ExitPorts {
      Port PASS CurrentExec.ExecResult==Pass {
        SetBin pass250MHz;
        Return;
      }
      Port FAIL CurrentExec.ExecResult==Fail { Next; }
    }
  }
  FlowNode test166MHz {
    TestNumber 12;
    Category cat166MHz;
    Selector selACSpeed;
    TestExec testFunc;
    ExitPorts {
      Port PASS CurrentExec.ExecResult==Pass {
        SetBin pass166MHz;
        Return;
      }
      Port FAIL CurrentExec.ExecResult==Fail { SetBinStop failFunc; }
    }
  }
}
TestProgram SpeedBin {
    ChannelMap DEFAULTPINMAP;
  EntryPoints {
    On Start MAINFLOW;
  }
}