[Fwd: Re: requiring hardware is futile]

[Bob Davis <Bob.Davis@xxxxxxx>]

Sorry for not watching the address line..


-------- Original Message --------
Subject: Re: requiring hardware is futile
Date: Thu, 20 Nov 2008 10:05:47 +0100
From: Arnold Neumaier <Arnold.Neumaier@xxxxxxxxxxxx>
Organization: University of Vienna
To: Bob.Davis@xxxxxxx
References: <200811171855.mAHItfg1009092@xxxxxxxxxxxxxxxxxxxxx> 
<49235503.6090603@xxxxxxxx> <49241C46.2030006@xxxxxxxxxxxx> 
<4924862B.2050501@xxxxxxx>

This seemed to go to me only instead of to the list.
Please resend...

Arnold

=========================================================================

Bob Davis schrieb:
> Arnold,
>
> Do you really care about how your operation is really performed? Do you 
> care if the operation is performed by dedicated gates in a processor, by 
> firmware on the processor, by HAL software, or by an interpreter layer?
>
> Different hardware vendors will, most likely, choose different ways to 
> achieve your functional requirements based on the their current internal 
> architecture, and planned architectural changes to meet their other 
> performance needs.
>
> The challenge of getting the major silicon vendors for processors, GPUs, 
> embedded systems, FPGAs and the compilers on the same page is a very 
> long job and a battle that you may not want to engage in.
>
> I would suggest that you solicit the response of the major silicon, et 
> al, vendors to respond to this proposal and what additional level of 
> detail would be needed for all of them to get you the same answer to a 
> set of operations.
>
> If you make IA popular, the vendors will make it fast to meet the need.
>
> Hardware vendors - please confirm or deny!
>
> Bob
>
> On 11/19/08 06:01, Arnold Neumaier wrote:
> > Bob Davis schrieb:
> > > IA, to be successful, will have to be a living implementation based 
> > > on the Standard and capable or surviving changing technology and 
> > > changing needs. If you required a specific hardware implementation, 
> > > it would: 1) become slowly obsolete based on new architectures and 
> > > processors; and 2) be extremely difficult to get the approval of the 
> > > larger group of experts that will serve on the sponsor ballot, 
> > > including, most likely, representatives of the various hardware, 
> > > silicon, and software implementors as well as other academicians 
> > > along with many members of this group.
> >
> > My next version of the proposal (to come end of this week or early next
> > week) will contain (only) the following about hardware support:
> >
> > Suggestions for hardware implementation:
> > A proposed minimal useful set of hardware operations which would
> > significantly speed up existing applications in constraint programming,
> > global optimization, and computational geometry are the following
> > operations defining core interval arithmetic.
> > - forward and reverse interval operations for
> >   plus, minus, times, divide, sqr
> > - mixed operations with one interval argument for
> >   plus, minus, times, divide
> > - forward sqrt, exp, log
> > - linearInt, linearExt, shiftedDivision
> >      [new proposed operations essential for computational geometry]
> > - mid, rad
> > - division with gaps
> > - optimal enclosure of inner product
> > These operations might be singled out to represent level 1 of
> > the standard; the remaining would represent level 2.
> > An appendix might suggest explicit model algorithms for these
> > operations.
> >
> > Could you please comment on this?
> >
> >
> > Arnold Neumaier


--
Respectfully,

Bob Davis
bob.davis@xxxxxxx
Cell 408.857.1273
Desk 33402/408.276.3402