RE: Suggestions for hardware implementation
Hi Paul,
In general, having instructions that issue multiple FP operations issue per
cycle (as is done with the SSE instructions) should help both interval
arithmetic and complex arithmetic. Interval arithmetic can also benefit from
fast rounding mode changes (or having rounding mode information included in
the instructions), as well as having fast support for detecting different
cases for interval multiplication and division. Complex arithmetic can
benefit further if more advanced instructions are supported (e.g., complex
multiply, complex multiply-add, complex divide).
My former students/advisor and I have done some work on hardware support for
interval arithmetic (and combined variable precision and interval
arithmetic). For example:
J. E. Stine and M. J. Schulte, "A Combined Interval and Floating Point
Multiplier," in Proceedings of 8th Great Lakes Symposium on VLSI, Lafayette,
LA, pp. 208-213, February, 1998.
http://mesa.ece.wisc.edu/publications/cp_1998-01.pdf
J. E. Stine and M. J. Schulte, "A Combined Interval and Floating Point
Divider," in Proceedings of the Thirty Second Asilomar Conference on
Signals, Systems, and Computers, Pacific Grove, California, vol. 1, pp.
218-222, November, 1998.
http://mesa.ece.wisc.edu/publications/cp_1998-02.pdf
J. E. Stine and M. J. Schulte, "A Case for Interval Hardware on Superscalar
Processors," in Scientific Computing, Validated Numerics, and Interval
Methods, pp. 53-68, Kluwer Academic Publishers, 2001.
M. J. Schulte and E. E. Swartzlander, Jr., "A Family of Variable-Precision,
Interval Arithmetic Processors" IEEE Transactions on Computers, no. 5, vol.
49 pp. 387-398, May, 2000.
http://mesa.ece.wisc.edu/publications/cp_2000-09.pdf
M. J. Schulte and E. E. Swartzlander, Jr., "A Processor for Staggered
Interval Arithmetic," in Proceedings of the 1995 International Conference on
Application Specific Array Processors, Strasbourg, France, pp. 104-112,
July, 1995. http://mesa.ece.wisc.edu/publications/cp_1995-02.pdf
M. J. Schulte and E. E. Swartzlander, Jr., "Hardware Designs and Arithmetic
Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor," in
Proceedings of the 12th IEEE Symposium on Computer Arithmetic, Bath,
England, pp. 222-229, July, 1995.
http://mesa.ece.wisc.edu/publications/cp_1995-03.pdf.
J. Stine, "Design Issues For Accurate and Reliable Arithmetic," Ph.D.
Dissertation, Lehigh University, 2001.
A. Akkas, "Instruction Set Enhancements for Reliable Computations," Ph.D.
Dissertation, Lehigh University, 2002.
Best regards,
Mike
--------------------
Mike Schulte
Associate Professor
Department of ECE
University of Wisconsin-Madison
1415 Engineering Drive
Madison, WI 53706
Office: 4619 Engineering Hall
Email: schulte@xxxxxxxxxxxxx
Office Phone: (608)-262-0206
Lab Phone: (608)-262-0940
Homepage: http://mesa.ece.wisc.edu
FAX: (608)-262-1267
-----Original Message-----
From: stds-1788@xxxxxxxx [mailto:stds-1788@xxxxxxxx] On Behalf Of Paul
Zimmermann
Sent: Tuesday, November 25, 2008 9:00 AM
To: J. Wolff v. Gudenberg
Cc: Arnold.Neumaier@xxxxxxxxxxxx; stds-1788@xxxxxxxxxxxxxxxxx
Subject: Re: Suggestions for hardware implementation
a random (maybe dummy) thought about hardware implementation: is it
possible to have hardware instructions that would be helpful both for
interval arithmetic (for the [lo, hi] representation) and for complex
floating-point arithmetic (for the cartesian representation)? If so,
this would increase the impact of such instructions, and maybe help to
convince the hardware vendors.
Paul Zimmermann