Re: Motion P1788/M007.01_NaI: Discussion period begins

[Nate Hayes <nh@xxxxxxxxxxxxxxxxx>]

I think NaI with payload would be practical. Branch-and-bound algorithms 
could use the payload information to avoid performing unnecessary bisections 
in some cases, for example.

Attached is a presentation Intel made at SIGGRAPH last year. It outlines in
some detail their new multi-core Larrabee architecture. The trend seems to
be convergence of GPU and HPC computing into new hardware architectures 
that
are both highly thread-parallel and data-parallel. For example, Larrabee not
only sports 16-48 cores (with each core supporting 4 hardware-managed
contexts), but each core also comes equipped with a 512-bit Vector
Processing Unit (VPU). In theory, this could perform 8 single-precision or 4
double-precision interval operations at a time.

While thread-parallelism is easy due to the embarrassingly parallel nature
of most interval algorithms, data-parallelism is probably an opportunity for
new interval research and may require some consideration. In my opinion,
sticky flags and traps are not friendly to this kind of computing
environment. It would be nicer to have a mode where flags are intrinsic to 
the interval datatype, i.e., NaI with payload, so they can propagate as 
needed for each individual element within the VPU .

Sincerely,

Nate Hayes

Attachment: larrabee_manycore.pdf
Description: Adobe PDF document