Re: Revised Motion 26 decoration scheme
On 2011-07-20 00:16:44 -0500, Nate Hayes wrote:
> Vincent, the scalability of high performance parallel computing on
> modern computer architectures is almost entirely determined by
> memory latencies and efficient usage of the cache hierarchy.
[...]
As long as you don't need a format for data interchange between two
different applications, this is not a problem. The compiler could
optimize to store data in some more optimized way than taking a
full 32-bit or 64-bit word for the decoration (e.g. by packing
decorations in a word). This would still be limited though, and the
language might allow hints given by the programmer (perhaps there
could be something in this direction in the P1788 standard), but
there aren't many solutions if you don't want to drop decorations
or make them "global" flags.
> There's really no way around the detrimental effects of this problem except:
>
> a) for modern hardware architectures to radically change
> b) to make sure our Level 4 datatypes fit nicely into power-of-two
> number of bits with no wasted storage
>
> I'm skeptical a) will happen anytime soon.
I suppose that concerning (b), you would want the size of a FP datum
to be reduced, so that it is possible to store the decoration in the
holes? That would require hardware changes and new formats that are
no longer IEEE-754 basic formats... This won't happen anytime soon
either, IMHO.
There's c: compiler optimizations and user compilation directives.
--
Vincent Lefèvre <vincent@xxxxxxxxxx> - Web: <http://www.vinc17.net/>
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Work: CR INRIA - computer arithmetic / Arénaire project (LIP, ENS-Lyon)