Hi Dan and the team,
As stated in BM meeting, I volunteered myself to provide the PAM draft. In the PAM consensus team we believe a serial scheme is the right option. I will work with the rest of the team to produce the right draft.
Sent from my iPhone
On Mar 25, 2013, at 12:13 PM, "Daniel Dove" <ddove@xxxxxxx
Thank you for sharing your opinion.
The Task Force chose to move forward with a draft development for
both a PSM4 (Pete) and CWDM (Petar) doing the work, on the
assumption that one of these approaches *may* see sufficient
consensus to achieve a baseline proposal adoption. PSM4 was
highest in the straw polling, and CWDM was next highest.
Anyone who has confidence that they can achieve consensus on an
alternative baseline proposal is asked to also produce a draft
clause so that we can leave the May meeting with a full draft set
of clauses to move forward with into Task Force review.
Clearly, LR4 and ER4 will be choices available to the industry in
a 4x25 CAUI-4 based solution. Whether or not they are sufficient
to address broad market needs over time will be defined by the
Chair, IEEE P802.3bm
On 3/25/13 11:39 AM, Ali Ghiasi wrote:
We had a very productive OFC meeting and hope you as well had
a productive IEEE meeting!
There were two interesting announcement at OFC with
implication to .bm SMF objective:
Finisar CFP2 100Gbase-LR4 PD< 7 W based on DFB DML
Cisco announces 100Gbase-LR4 CPAK OFC demo based on Silicon
Photonics with PD < 5.5 W
Above 100GBase-LR4 products in live demo during OFC-2013 have
power dissipation lower than power quoted in some of the IEEE
PSM4 does not offer cost advantage of 0.23-0.13 as was
illustrated with PAM solution
It is clear that in the .bm group the solution based on
serial 100 Gb/s with best economic and cost advantage
require more time to converge to a baseline proposal than we
have in the bm group. IEEE already has the Cadillac solution
the 100Gbase-LR4 and I believe nearly everyone in our task
force would agree the ultimate solution is serial 100 Gb/s and
something we have to define in the 400 GbE, but we may disagree
on the timing. If we can't agree to define the ultimate
solution now, do we wait or do we define something between the
Cadillac and the ultimate solution that may only have short term
market potential ?
I would definitely support both CWDM and PSM4 as part of an
On Mar 25, 2013, at 10:16 AM, Daniel Dove wrote:
Thanks for bringing this up.
All, when producing questions on a presentation please
be attentive to the fact that we participate on an
individual basis and frame your questions to the
individual, not their employer or affiliation.
In the same manner, if someone asks you a question
directed to your employer or it's business, or any other
business for which you may have information that is
proprietary, do not feel obligated to respond.
Chair, IEEE P802.3bm
On 3/25/13 9:57 AM, Brad
a bit concerned about this line of questioning and
some of what I noticed happening at last week’s
meeting (at least the portion I was able to
seems to be a lot of focus on vendor-specific
implementations which then trends into the realm
of cost comparison, NDAs, and opinions on
goal of the task force is to develop a standard
written such that it is not dependent on any
implementations, but rather that it enables
multiple, interoperable, compliant
it possible to put the relative cost comparison
and vendor-specific implementation information
aside and focus on the market requirements and
technical merits of each proposal?
As a follow-up on yesterday’s discussion I am
summarizing here questions to the presentation
Some of the questions I was able to ask during the
Q&A time, while some of them were left
unanswered or even not asked due to request of the
Chair to move the rest of the discussion offline.
Following Chair’s suggestion I am writing down all
the questions I was planning to ask here in the
Reflector. I do believe that it is important for
people on the floor to get an unbiased view on
advantages and disadvantages of various proposals as
well as on technologies behind them to cast a
balanced educated vote.
The answer on the first question is crucial. I would
have had no further questions if the answer would
have been “Yes”. However the answer was “No”.
Correspondingly I feel obligated to present here all
the questions numbered consecutively with the page
number in the presentation listed for the reference.
Do you agree or do you not, “yes” or “no” would
suffice, that “Si Photonics” in the title of your
presentation means “Luxtera Si Photonics technology”
and, correspondingly, the numbers and statements
presented are related to advantages and
disadvantages that Luxtera technology has in trying
to reach performance required by different baseline
This page represents the strategy for comparative
analysis of link budget, power, assembly and cost
for CWDM, PSM4 and LR4. Depending on how this
strategy is formulated a substantially different set
of conclusions can be reached.
It is stated that for power estimate the “fully
integrated silicon photonics solution using 28nm
CMOS node” is being used. Does “full integration”
means CMOS circuits and optical devices located
side-by-side on the same silicon die?
What is the level of maturity of this “fully
integrated silicon photonics 28nm CMOS technology” –
a) is it in development, b) is it fully qualified
or, by any chance, c) does Luxtera already have
transceiver (not AOC) products shipped today in
volumes with this technology node?
In this page you mention “existing silicon photonics
technologies”. Which existing silicon photonics
technologies are you considering: a) Luxtera
technology exercised in 130nm node at Freescale, b)
Luxtera 28nm technology mentioned above, c) any
other Luxtera technology not mentioned or d) Si
Photonics technologies of other companies?
If the answer to Q4 is “all of the above”, what are
the sources of your information and what is the
approach you are using in assessing the non-Luxtera
Si Photonics technologies?
Which technology version of Luxtera Si Photonics
technology the performance numbers of WDM mux and
Demux correspond to – a) the 130nm Freescale or b)
“fully integrated silicon photonics 28nm CMOS node”?
How different is the interleaver presented on the
right bottom corner of this page from the one
reported in T.Pinquet et al, Proc. of SPIE Vol.
6898, 689805, (2008) with 2.6dB insertion loss?
Are you aware of other reports on low-loss and
passive (no tuning power required) WDM filters
demonstrated in a number of non-Luxtera Si Photonics
For example, are you aware of several presentations
presented in the past at this IEEE 802.3bm as well
as in the 100G Study Group meetings on WDM filters
based on non-Luxtera Si Photonics technologies that
have less than 3dB insertion loss:
pages 9 and 10 in
page 12 in
page 6 in martin_01_0712_optx.pdf
page 4 in vlasov_01_0312_NG100GOPTX.pdf ?
Are you aware that of these WDM devices listed in Q9
(in addition to many other silicon photonics WDM
demonstrations currently in the public domain) NONE
are relying on active thermal tuning of the WDM
components phase and hence do not contribute to the
total dissipated power as it is demonstrated, for
example, on page 10 of
Are you aware that all of these measured results
listed in Q9 are obtained on chips fabricated on a
high-volume non-Luxtera Si Photonics technology
platforms in Kotura or IBM?
Do you agree that the necessity to burn a total of
1.8W of power for tuning of WDM components as
suggested in page 4 is not a generic problem with
all Si Photonics technologies, but rather, perhaps,
a problem with one of Luxtera’s Si Photonics
technologies? Which one?
Does the “PSM4”, “CWDM” and “LR4” on the top of each
column have any relation to corresponding baseline
proposals as it was presented at the latest meetings
of 802.3bm (anderson_01a_0313_optx.pdf and
The usual approach to calculate the optical power
link budget that 802.3 has followed for many years
is to calculate the channel insertion loss between
TP2 and TP3 and add the TDP penalty. For all IEEE
standards this link budget does not include
insertion loss of the transmitter or receiver. These
latter numbers are left for vendors to resolve and
are not a part of any standard.
If the Q13 answer is “yes” then do you agree that
the link budget calculations should follow the usual
definition as channel insertion loss plus TDP
penalty for 500m channel reach as presented for all
PMD baseline proposals so far?
If the answer to Q13 is “yes” and the “CWDM” column
represent an attempt to build a channel insertion
loss budget based on the 100GBASE-CWDM baseline
vlasov_01a_0313_optx) , why 2km option is used
on line 4 with additional 0.75dB insertion loss,
while the objective of both the 802.3bm TF and the
baseline CWDM proposal is the reach up to 500m?
If the answer to Q13 is “no” this means that columns
“CWDM” does not refer to a specific baseline
proposal. It is possible then to assume that the
table represents an attempt to fold module insertion
loss into the link budget and compare to other
In this case, if the answer to Q4 is “all of the
above” and the answer to Q9 is “Yes” then why
additional 3dB+3dB=6dB insertion loss due to MUX and
DMUX is included for “CWDM” column since it is a
problem specific only to one or all of Luxtera
technologies in yielding low loss WDM, and this
generalization is not applicable to all possible
non-Luxtera Si Photonics technologies?
If the answer to Q13 is “yes” and columns “PSM4” and
“CWDM” correspond to PSM4 and CWDM baseline
proposals as presented in
then the bottom line of the table representing “per
baseline proposal (aggregate)” corresponds to
maximum channel insertion loss. Correspondingly, for
the baseline PSM4 this should be 3.26dB and for the
baseline CWDM should be 4dB. Correspondingly, the
difference in channel insertion loss between PSM4
and CWDM baseline proposals should be 0.74dB, not
7dB. With maximum TDP budgeted differently (for
baseline PSM4 as 3.8dB and for baseline CWDM as
2.2dB) the total power link budget for maximum TDP
is actually 7.06dB for PSM4 and 6.2dB for CWDM. Do
If the answer to Q1 is “Yes” there are no comments
related to pages 8, 9, 10, and 11 since it solely
represents numbers for Luxtera “fully integrated
silicon photonics solution using 28nm (or better)
CMOS node.” The maturity level of this technology is
already answered in Q3. If the answer to Q1 is “No”
– then there is a question: Which version of
non-Luxtera Si Photonics technology (and from which
company) is used to fill out the columns “CWDM” and
“LR4” in pages 8, 9, 10, and 11?
There is a subnote “Achilles heel of CWDM”. Which
non-Luxtera Si Photonics technologies are having
Which non-Luxtera Si Photonics technologies are
having these problems?
For example edge coupling technologies are, in fact,
widely used for edge emitting lasers iii-V PICs,
etc. for many decades. Some of non-Luxtera
Si-Photonics technologies successfully using edge
coupling for volume products, like for example VOA
and other components from Kotura. It is, actually,
vertical grating couplers that Luxtera technology is
using that is a relatively new and to my knowledge
unique approach for coupling light in and out of the
In general, it is possible to imagine that
non-Luxtera Si Photonics technologies utilizing edge
coupling might not necessarily suffer from violation
of CMOS design rules, do not require CMOS
post-processing (precision dice/polish), can enable
easy fiber attach, and do not require large area for
bonding to CMOS.
If Luxtera Si Photonics technologies are being used
for comparison it would be good to know which
version of the technology a) 130nm Freescale or b)
“fully integrated silicon photonics solution using
28nm (or better) CMOS node” is being considered?
If it is a) then indeed millions of parts were
shipped and edge coupling was not in production and
is only theoretically known. If it is b) then it is
necessary to refer to the answer to Q3 and apply it
here with respect to the statement “millions of
grating couplers already shipped”.
What the source of the information that non-Luxtera
Si Photonics technologies using edge coupling are
having a problem of “prohibiting chip on board cost
What the source of this information that non-Luxtera
Si Photonics technologies that are using edge
coupling are having to rely on “polarization
If the answer to Q1 is “No” and the statements on
this page also include comments on non-Luxtera Si
Photonics technologies, then the word
“theoretically” should be removed since numerous
feasibility demonstrations have been presented in
the open public domain showing monolithically
integrated WDM mux, Demux, photodetectors,
modulators, etc. that can be found for example in
the proceedings of the OFC from 2007 to 2013. I can
easily provide over 50 recent references upon
If the answer to Q1 is “No” and the statement on
this page 14 “Insufficient technology maturity to
reasonably project costs/yields” also includes
comments on non-Luxtera Si Photonics technologies,
then I would insist on rephrasing the statement to
“Insufficient information that Luxtera has on
technology maturity to reasonably project
It is a critical page in the presentation as it
compares module costs for various implementations.
If the answer to Q1 is “Yes” then don’t the
statements in this comparison refer to problems
specific to Luxtera Si Photonics technologies, and
as such this comparison illustrates that Luxtera Si
Photonics technologies could not provide CWDM
modules in a cost-effective manner.
If the answer to Q1 is “No” then the statements in
this comparison implies generalization of problems
specific to Luxtera technologies to all other
non-Luxtera Si Photonics technologies. In this case
I would ask which non-Luxtera technology is used for
this comparison and what the source of this
information is. I would also suggest to take into
account three independent relative cost analysis
studies presented in
shen_01a_0313_smf and in
Statements on this page either refer to Luxtera Si
Photonics Technologies (if the answer to Q1 is
“Yes”) or (if the answer to Q1 is “No”) it is
required to provide additional information as
mentioned in all related questions above.