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RE: SONET/Ethernet clock tolerance

Title: RE: SONET/Ethernet clock tolerance


Regarding the subset of SONET/SDH overhead functionality required by the
proposed WAN-Compatible PHY: this has been described in

and, in greater detail, in

Some of the functions that are NOT needed by the WAN-Compatible PHY that
would normally be required by STS-192 PTE are (the most significant are marked
with an asterisk):

Section Orderwire (E1) insert / extract
User Data (F1) insert / extract
Section DataComm (D1-D3) insert / extract
*383 STS pointer processors (192 in each of Tx and Rx direction normally required)
*384 Line BIP-8 (B2) generators (this is a big chunk: > 6144 bits of high-speed storage)
*192 Line BIP-8 extract / compare and B2 mis-match accumulator (~ 1600 bits of storage)
Line APS bytes (K1/K2) extract / validate
Line DataComm (D4-D12) insert / extract
Synchronization Status Message (S1) extract / validate
Line REI (M1) extract / accumulate
Line Orderwire (E2) insert / extract
Path Trace (J1) extract / message assembly / Trace Mismatch compare
Path BIP-8 (B3) modification to support Tandem Connection
Path User (F2) insert / extract
Path Multiframe (H4) insert / extract
Tandem Connection Maintenance (N1) insert / extract

In addition to these data-path insert / extract functions are the corresponding processing
functions and management registers, which are also NOT required.

Conversion to power-dissipation/gate-count/etc will depend on partitioning and process.

Tim Armstrong
Nortel Networks