IEEE P1149.4 Mixed-Signal Test Bus Working Group
Meeting Minutes


November 2, 1997

Generously sponsored by Matsushita

Access the Minutes of the June, 1997 Working Group Meeting.

Meeting Agenda

Time Topic Responsibility
8:00am Breakfast - Thank you Matsushita
8:30am Arrival and Introductions Adam Cron
8:45am Approval of June, 1997 Minutes Adam Cron
9:00am Draft Review Brian Wilkins
10:30am Break
10:45am Draft Review - Continued Adam Cron
12:00pm Adjourn for Lunch
1:30pm Draft Review - Continued Adam Cron
3:00pm Break - Thank you Matsushita
4:45pm New Measurement Method Steve Sunter
5:05pm Ballot Status - What Next Adam Cron
5:35pm 1149.1 Status Ken Parker
5:45pm Next Meeting Adam Cron
6:00pm Adjourn Adam Cron

Working Group Statistics

Working Group Members 31ish
Total Subscribers 426
Total Subscribers on "esd" reflector 429
Countries Participating ~32
Companies and Other Institutions Participating ~250
Funds Available ~$550

Meeting Attendees

Name Company Sponsor
Karim Arabi Opmaxx
John Andrews National Semiconductor
Adam Cron Synopsys
Dan Dandapani University of Colorado
Frans de Jong Philips
Carrel D'Haiti National Semiconductor
Ted Eaton Intellitech
Firooz Farhoomand Matsushita
Joel Goldberg Test & Measurement World Magazine
Katsuhiro Hirayama Panasonic Semiconductor
Terry Junge Seagate
Adam Ley Texas Instruments
Keith Lofstrom KLIC
Colin Maunder BT Laboratories
John McDermid Hewlett-Packard
Kozo Nuriya Panasonic Semiconductor
Adam Osseiran Ecole D'Ingenieurs de Geneve
Ken Parker Hewlett-Packard
Paul Pilotte GenRad
Adam Sheppard ASSET InterTech
Mani Soma University of Washington
Steve Sunter LogicVision
Tony Suto GenRad
Lee Whetsel Texas Instruments
Brian Wilkins Southampton University

Sending Regrets

Name Company Sponsor
Terry Borroz Teradyne
Ed McCluskey Stanford University
Michel Parot Thomson-CSF

Ken Parker (KP) Motion: To accept the minutes of the previous meeting. Steve Sunter seconded. Vote: unanimously in favor - motion passed.
(KP) Motion: "We will not add any more 1149.1 tutorial to the document." Frans de Jong seconded. Vote: 10 in favor, 1 opposed, 0 abstain. Motion passed.
(KP) Motion: "We don't make a change regarding the visibility of AB1 and AB2." Mani Soma seconded. Vote: unanimously in favor. Motion passed.
Dan Dandapani (DD) Motion: "Delete rules 4.2.3(a) and 4.2.3(b), add a preamble statement to 4.2.3: 'Test controller ...', leave rules 4.2.3(c) and 4.2.3(d) as-is, add a dotted line in Figure 7 to show the test controller." This motion did not receive a second.
(SS) Motion: "All 1149.1 and 1149.4 consistency issues are to be addressed by e-mail." Brian Wilkins seconded. Vote: unanimously in favor. Motion passed.
(BW) Motion: "Delete rule 7.3(b)." Steve Sunter seconded. Vote: unanimously in favor. Motion passed.
(?)Motion: "Delete last sentence of the Description in 7.3.3 on page 61." Seconded. Vote: unanimously in favor. Motion passed.
(CM) Motion: "Move 8 to Annex." Seconded. Vote: 1 opposed. Motion passed.
Keith Lofstrom (KL) Motion: "Add sentence to 8: 'This chapter is for information purposes only and contains no rules.' or something to that effect." Mani Soma seconded. Vote: 8 in favor, 2 opposed, 4 abstain.
Mani Soma (MS) Motion: To adjourn the meeting. Adam Sheppard seconded. Vote: unanimously in favor. Meeting adjourned.

Arrival and Introductions

Meeting began at 8:30 AM with a roundtable introduction of all.

Approval of June, 1997 Minutes

Ken Parker (KP)
Motion made to accept the minutes of the previous meeting. Steve Sunter seconded. Vote: unanimously in favor - motion passed.

Draft Review

Brian Wilkins (BW)
There were about 280 ballot comments, mostly editorial.

All agreed to forward all editorial comments directly to Brian for processing.

(BW) A key issue is the relationship of 1149.4 with 1149.1. For example, Negative ballot comment 9 (Neg#9) page 11, 2 is a direct quotation from the IEEE style manual.

Colin Maunder (CM)
The problem is also with the non-approval of 1149.1. The IEEE rule is nonsense and needs to be changed. It needs to be brought to the overview meeting. Recommend removal of .1-specifics or relocation of the .1 items away from the rest of the rules. Describe .4 as an add-on, not as a complete standard, so that .4 requires conformance to two standards.

(KP) .4 can't do that because it contradicts .1.

Adam Cron (AC)
We expect changes in .1 to resolve this contradiction.

Steve Sunter (SS)
Need to minimize change to this draft of .4 to avoid attracting unnecessary comments in the next ballot.

(AC) The objective is to get the three negative ballots changed to affirmative on the reballot.

(CM) Can we rewrite to avoid the fact that .1 is changing to who knows what? Can do one of two things: presume that the change to .1 is fated, or write .4 as .1 is today, for example, SAMPLE/PRELOAD, and include explanatory note that a split of the instructions is expected.

(BW) Suggest that we do the latter [use explanatory notes for expected changes].

(CM) That's acceptable.

(KP) I have a feeling that we need to report this at the IEEE Test Technology Steering Committee meeting.

John Andrews (JA)
Another problem: requirement of .1 that digital/analog circuitry needs a DBM to separate the digital from the analog could cause specification lawyers to reject the standard.

(BW) In short, we need to push forward with this compromise.

(SS) Comments assigned to Brian Wilkins are at his discretion.

(CM) Suggest negative ballot comment form (Appendix B) be used as the basis for the negative ballot responses.


(BW) Redo last sentence of 3.9, replacing "boundary-scan register cells" with "boundary-scan structures".


(KP) "In-situ test" was originally suggested to give the document an international flavor.


(BW) Don't understand the comment.

(SS) The problem is that we don't want zero impedance.

(KP) These switches are many orders of magnitude higher impedance than mercury switches and it's OK. It's a reality at the chip level.

(BW) This is explained in Note 1 of 3.23.

(CM) We could add a forward reference: "see chapter 9 for more information".

(BW) We can't do that, because the definitions get moved to IEEE Std 100.

Adam Ley (AL)
It is acceptable for IEEE Std 100 to have a definition that references another specification.


(AL) Need to make it clear that a unidirectional switch may be used.


(BW) Why incorporate this comment?

(CM) The 1149.4 document is a stand-alone document then, not an add-on to 1149.1.

(KP) Motion: "We will not add any more 1149.1 tutorial to the document." Frans de Jong seconded. Vote: 10 in favor, 1 opposed, 0 abstain. Motion passed.


(KP) Parametric effects in the analog world make the presence of AB1 and AB2 known.

(AC) Change "minimally compliant" to "minimally configured" in the caption for Figure 5.

(KP) Motion: "We don't make a change regarding the visibility of AB1 and AB2." Mani Soma seconded. Vote: unanimously in favor. Motion passed.


(CM) Wording is "like 1149.1", not "is 1149.1".

(AL) Say "1149.1" first.

All Some discussion followed centered on 4.2.1 - is it saying something more than 1149.1 is required or not?

(AC) Can we resolve this issue by moving or confirming rules are elsewhere?

All The consensus was "yes", but more discussion followed.

Lee Whetsel (LW)
To reduce confusion, I suggest we update figure 7 to show the "Test Controller" block that is shown in figure 5.

Dan Dandapani (DD)
Motion: "Delete rules 4.2.3(a) and 4.2.3(b), add a preamble statement to 4.2.3: 'Test controller ...', leave rules 4.2.3(c) and 4.2.3(d) as-is, add a dotted line in Figure 7 to show the test controller." This motion did not receive a second.

(KP) Need to show the bypass register in Figure 5 - it is not a part of the 1149.1 TAP.

(SS) Motion: "All 1149.1 and 1149.4 consistency issues are to be addressed by e-mail." Brian Wilkins seconded. Vote: unanimously in favor. Motion passed.

(CM) I suggest a small group approved by the working group to address these consistency issues.

(AC,SS) No. Brian heads this up.

(BW) Action: coordinate 1149.1 consistency issue cleanup.


(BW) I didn't understand this comment.

(SS) 1149.1 does not preclude a DBM on analog pins.

(KP) Reject this comment because these pins are not part of 1149.1.


(?) Replace "AT1 and AT2" with "all ATAP pins" in rule 4.3(c). Keep permission 4.3(d).

(CM) Change 4.3(b) to say at least two analog test pins.

(AL) Not "at least".

All The consensus was to only allow two or four pins. Three pins are not allowed - at the Seattle meeting in spring 1997 this was explicitly motioned out.

(SS) What about the 1149.1 compliance enable requirements - do they apply to 1149.4?

All The consensus was "yes".

(BW) I suggest inserting the word "Additional" before "Rules".

All The consensus was "no".

(LW) Can we consolidate the 1149.1 interface at the front of this specification?

Mani Soma (MS)
The document would be very different and would contradict the earlier motion (re: no more 1149.1 tutorial).


There was a review of the intent of 1149.1 INTEST versus 1149.4 INTEST.

(CM) [Colin drew exhibit 1, recreated here.]

Exhibit 1. INTEST diagrams

(CM) Is 1149.4 INTEST OK as-is? Or must it be a new instruction and the old INTEST fully control the analog test boundary? Problem: capture on INTEST is undefined.

All General discussion followed regarding reasoning behind 1149.4 INTEST definition.

(KP) We need permissions to amplify these capabilities.

(KP) Action: help Brian Wilkins write these permissions.

At this point, the working group adjourned for lunch.

All Agree that, in the interests of time, we concentrate on the starred comments in the negative ballot list only. These comments were the reason why the three negative ballots were negative.


All The group agreed with the comment.


(KP, CM, MS)
Replace "internal bus line" with "AB1/AB2". Replace "both ATAP pins" with "any ATAP pin".


(SS) Problem: I need to sell an MCM that is labeled an "1149.4 compliant chip". I can't do it. Should we allow multiple TBICs? Should we allow multiple AT1/AT2 pin groups? 1149.1 is the problem - the MCM has multiple TAPs.

(LW) There may be a problem with embedded analog signaling - not likely.

(AC) A quick fix here may be risky. It could be abused.

(SS) I withdraw the negative comment.


(BW) I suggest deleting 7.3(b).

(KP) [Ken drew exhibit 2, recreated here.]

Exhibit 2. Core disconnect figures

(KP) If the receiver is high impedance, may be that no core disconnect is needed [subfigure 2], or it may be integrated into the driver [subfigure 3].

(BW) Motion: "Delete rule 7.3(b)." Steve Sunter seconded. Vote: unanimously in favor. Motion passed.


(BW) The comment is inaccurate due to the presence of user-defined instructions.

(CM) The designer could also choose not to encode. He could use four wires instead of two. He needs at least two mode lines as demonstrated by Table 9.

(?) Motion: "Delete last sentence of the Description in 7.3.3 on page 61." Seconded. Vote: unanimously in favor. Motion passed.


(KP) We need the naming of control register stages because we're adding new cell types to BSDL.

[Negative ballot comment withdrawn.]


(CM) There are no rules in clause 8. Mark the text as explanatory, or move it to an Annex and begin clause 9 with a forward reference to the Annex.

(CM) Motion: "Move 8 to Annex." Seconded. Vote: 1 opposed. Motion passed.

Keith Lofstrom (KL)
Motion: "Add sentence to 8: 'This chapter is for information purposes only and contains no rules.' or something to that effect." Mani Soma seconded. Vote: 8 in favor, 2 opposed, 4 abstain.


(SS) I discard my proposal; instead let's address the problem. I suggest a permission that not both have to be driven to the same value. Put information in BSDL so tools know whether or not this is done.

(KP) The differential PIN_GROUPING in BSDL can be a clue.

(SS) Yes. Then the chip designer could put tristate controls on each output side and he's done.

(AC) [Adam Cron drew exhibit 3, recreated here.]

Exhibit 3. Differential I/O picture vs. implementation

(SS) [Steve Sunter drew exhibit 4, recreated here.]

Exhibit 4. Differential I/O implementation

(SS) If you try to put both pins of the differential I/O low or both high in this implementation, they won't do it. They do halves.

(JA) [John Andrews gave his presentation entitled "Digital Differential I/O: P1149.1 WG & 1149.1 WG Meetings ITC '97". This is available as a separate document.]

(AL) Define VL as 1/2 level to compensate. [There was general dissent to this suggestion.]

All Action: resolution by e-mail.


(BW) I agree that Figure 23 is not referenced. I will add a reference.

Neg#92, 93

Action: resolution by e-mail.


(BW) Agreed. Will change "six" to "have five" and remove "IT".


(BW) Add sentence "The measurement error ..." to explain the 1% error requirement. [to be defined by Steve Sunter]


All Action: fix high impedance definition by e-mail to resolve this.

Neg#100, 104


At this point, the group began addressing both affirmative and negative ballot comments. None of these were asterisked, so only the hot spots were addressed. Comments not addressed are at Brian Wilkins' discretion.

Aff#20, 22, 23

Communication problem? VG must be available at a pin, but this is not in the specification except in the definitions and documentation requirements.

John McDermid (JM)
Action: John to address this problem.

Aff#38, 40, 51, 52

Agreed. Add or expand the rules to address these comments. Add pins to ATAP rules.


Some discussion or whether to delete the note. The consensus was to delete it.


(KP) The specification should have a forward reference to 7.3 where the ABMs are described.


After some discussion, the group agreed to clarify with rules in 9.4, and a forward reference from 6.3.

(SS) Use e-mail to handle additional text defining "high impedance" to mean "no active internal AC or DC sources".


Consensus was that there will be no problem in BSDL. Leave unchanged.


(KP) Pare down rule 6.4(e) and fix so that the Update latch may be on either side of the decode logic in the figure. 7.3.3(d) is similar. This is not simple if the update register is on the other side because Update-IR may cause a change on the device pins; for example, when the current instruction is PRELOAD and a new instruction EXTEST is shifted in.


Consensus was that the specification is OK in spite of this. Add a forward reference to 9 to clarify this.


Agreed. Change per comment.

Aff#142, 147

(JM) It seems that the reviewer thought that the 3dB point was in the acceptable range and it is not. We put considerable effort into the specification to make the bandwidth wider, but the reviewer missed it.

(SS) Action: do diagrams to show models used for metrology and fax to Brian Wilkins.


(AL) This requirement needs a reasonable duration.

(CM) 1149.1 has the same problem.

(AC) This is not any worse than turning on a faulty circuit.

(AL) The problem is not the crummy switches, but the conceptual switch from the functional driver. If the rule is clarified, then it is OK. Generally, IC vendors specify a maximum one (1) second short either to ground or rail.

(AC,SS) The rule meant the crummy switches.

(JM) You don't want a short to destroy the test circuitry.

(SS) We want the test circuitry not to die before the functional circuitry.

(KP) We want to specify this. Enumerate the test switches.


(BW) Why does RDC have a switch? This is a conceptual problem since we say there is no connection, but with a resistor we have a connection.

(SS) We have a better way:

[Steve Sunter drew exhibit 5, recreated here.]

Exhibit 5. Use voltage drivers, not current drivers

All The idea was accepted.

New Measurement Method

This was Steve Sunter's exhibit 5 shown earlier.

Ballot Status - What Next

All agreed to have e-mail resolution on items within two weeks.

1149.1 Status

The 1149.1 ballot is expected early next year.

Next Meeting

The next meeting is tentatively scheduled for March 2-3, 1998. The hope is to finalize the date for the end of February or the beginning of March. HP-Loveland and TI-Dallas are possible locations to be confirmed.


Mani Soma moved to adjourn the meeting. Adam Sheppard seconded. Vote: unanimously in favor. Meeting adjourned.

# Location Comment
1 Page 1, Abstract Change "...of control and access for ..." to "...of control of and access to ..."
2 Page 2, Introduction, para 3 Reword as follows (note subtle differences!) -"The work received the support of ... November 1991, following which ..." Also, please delete the affiliations of Mani Soma and Adam Cron. It is inappropriate to include these only for selected individuals.
3 Page 6, 1 Change to "... other published material necessary for ... while clause 3 defines terms and acronyms. Clauses 4 to 8 specify the implementation of this standard and provide descriptive material to illustrate ..."
4 Page 6, 1.1 Change to "This standard defines test features that may be ..." (There is no compulsion!)
5 Page 7, 1.2, para 1 Delete "The existing". In line three, you include "analog". However, the scope on page 6 does not include pure analog devices.
6 Page 7, 1.2, Figure 1 Please add legends to this figure (e.g., make it clear what the gaps in lines, blobs, etc are.
7 Page 7, 1.2, first of many instances Abbreviate IEEE Std 1149.1 consistently. In some places it's "IEEE Std. 1149.1" and in others it's "IEEE Std. 1149.1". IEEE Std 1149.1 does not use the period. Change "IEEE Std. 1149.1" to "IEEE Std 1149.1" (throughout).
8 Page 8, 1.2, top para In the sentence "Meeting this objective ..." you do not make it clear that the components need to be associated with analog, digital, or mixed signal components that conform to this standard.
9 **Page 11, 2 "When the following standards are superseded by an approved revision, the revision shall apply." This is absolute nonsense, even if it is mandated text from the IEEE. For example, changes in 1149.1 after publication of 1149.4 could render all the references to 1149.1 useless. Worse, 1149.1 could change in a way that is not supportive of 1149.4. This document will make sense only if it refers to a specific version of 1149.1.
10 Page 12, 3.1 "the core" should read "the core circuit". The reference should also be to "core circuit"
11 Page 12, 3.2, Note 1 Replace "opamps". Avoid colloquialisms.
12 Page 12, 3.2, Note 2 Add "core circuit" to reference list. Change "core" to "core circuit" at the end of the note itself.
13 Page 13, 3.9 "between the core circuit and"
14 Page 13, 3.9, Note 1 The last sentence of 3.9 says "same" while the note says "different". Which is it?
15 Page 14, 3.15 "in-situ test" and "bed of nails test" are not defined terms
16 Page 15, 3.23 "very low impedance" - Might the use of "very" be misinterpreted? How is "very" defined?
17 Page 16, 3.23, Note 3 Its not clear from the last sentence if the highlighted situation is acceptable or not. Note 2 seems to suggest it is. Please make this clear.
18 Page 17 Should "Voltage source symbols" be a heading?
19 **Page 18, 4 I find the continual references out to 1149.1 that start here most confusing. I strongly suggest that Clause 4 be split into two clauses. The first should include only rule 4.1a, accompanied by a tutorial review of 1149.1. The review's purpose is to make this standard sufficiently free-standing that you don't have to have two documents in your hands to make sense of it. (See below re rewording of 4.1a.) The second should highlight the architectural differences to 1149.1. (At present, it is an interesting blend of restatement of 1149.1 material and new stuff.)
20 Page 18, 4.1a Reword to "Components claiming conformance to this standard shall deviate from the rules set out in IEEE Std 1149.1 only as specified in this standard." (Avoids "apart from exceptions - double negative!)
21 **Page 18, Figure 5 This figure marks the arrival of several new players in this document, including AB1 and AB2. I am far from sure that you can tell whether or not any of the rules about inclusion of these lines and their operation have been implemented or not just by looking at the outside of the component. The problem is that much of the standard is written from the component designer's viewpoint and not from the purchaser's viewpoint. It should be written from the latter - i.e., you should specify things as they appear, not as they are built.
22 Page 19, 4.2.1 This paragraph is a rule, but is not labeled as such.
23 Page 20, 4.2.2, para 1 This is a rule, but is not labeled as such.
24 Page 21, 4.2 The text uses ideas that have not been introduced yet to explain a statement. I found this unclear on first reading. Delete "because each boundary module contains its own control register".
25 Page 21, 4.2.3, Rules c and d "boundary register bits" This term is not defined. Use "ABM control registers" as in the description.
26 Page 21, Description, last para "All the digital boundary modules described in IEEE Std 1149.1 ..." - None are described in 1149.1! Also, "require control signals ..." - none of these signals is required by 1149.1.
27 Page 22, 4.3, Rule c If these are dedicated test pins, I think that this means that 1149.1 precludes them being equipped with boundary-scan test capability. However, they are so equipped (for EXTEST).
28 Page 22, Permission d Must AT1N and AT2N be dedicated if they are provided? If so, change rule © to say that all ATAP pins shall be dedicated.
29 Page 22, 4.4, above fig 7 "... and it must confirm ..." - This is a rule. It is also the same rule as 4.1a. Delete it - you don't need to keep highlighting this.
30 Page 22, Figure 7 Does not show AT1/2 or AB1/2 or TBIC
31 Page 23, Description Here is an example of how, given that the "built on top of 1149.1" rule has been stated, other text can be simplified. Delete the description in its entirety - it doesn't say anything that the first part of 4.4 doesn't.
32 Page 24, 5.1, Rule a Delete - covered by the "In addition to the rules defined in ..." preface.
33 **Page 24, 5.1, Notes to Rule a The current version of the body of 1149.1 is 1149.1a-1993. These notes refer to an unballoted draft of 1149.1, which may or may not pass ballot at a later date. For now, this document must be written on the basis of what is already approved, not what may be approved in the future. Revert to SAMPLE/PRELOAD or, better still, delete the notes along with rule a.
34 Page 24, 5.1, Rule c Delete. Covered by "based on 1149.1" rule and preface statement. (Also, not compatible in existing form with current version of 1149.1. This also requires all-0s to be reserved for EXTEST.)
35 Page 24, 5.1, Permission e Delete. Covered by "based on 1149.1" rule and preface statement. (Also, not compatible in existing form with current version of 1149.1. This also requires all-0s to be reserved for EXTEST.)
36 Page 24, 5.1, Note to Permission e This should be a permission, not a note
37 Page 25, 5.2 Delete this clause. Covered by the "based on 1149.1" rule. Also note that rules a and b do not between them require any support for the PROBE instruction.
38 Page 26, 5.3.1 Must add "In addition to the rules ..." preface at start of Rules sub-clause. Note missing Description sub-clause heading.
39 **Page 26-27, 5.3.2 and 5.3.3 Same comment as for 5.3.1. In addition, to ensure conformance with the current published version of 1149.1, these clauses must be merged into one that addresses SAMPLE/PRELOAD.
40 Page 27, 5.3.4 Must add "In addition to the rules ..." preface at start of Rules sub-clause. Delete rule a - covered by preface statement. Delete "the" between "support" and "measurements" in the Note. Delete the last paragraph from the description on page 28.
41 Page 28, 5.3.5 Add note to rule b to compare this with the situation that pertains for SAMPLE/PRELOAD or BYPASS. Add a rule to require AT1 and AT2 to be connected to AB1 and AB2.
42 Page 29, 5.4 Delete the second sentence "If any of these instructions ..."
43 Page 30, 5.4.1 Add "In addition to ..." preface to rules sub-clause. Move note 2 to rule c to be a note for rule b. Explain note 1 to rule c. "Because there is only one analog test bus line available ..." What? I thought there were two - AT1/2.
44 **Page 30, 5.4.1 Where is the equivalent of rule b in 5.4.3?
45 Page 30, 5.4.1, NOTE 2 Unclear. Change "notice that the core is connected to the external circuitry." to "notice that much of the core is not isolated from external circuitry." Should the standard also mention that care should be taken to ensure that the core itself should not generate unwanted interference?
46 Page 31, 5.4.1, last para Why refer to AB1/2 - signals that no-one can access? Rewrite referring to AT1/2.
47 Page 33, and Delete. Restatement of 1149.1.
48 Page 33, 5.4.3 Add preface statement ("In addition to ..."). Delete rule a.
49 Page 34, 5.4.4 Add "In addition to ..." preface to rules sub-clause. Insert missing Description sub-clause header.
50 Page 34, 5.4.5 Add "In addition to ..." preface to rules sub-clause. Insert missing Description sub-clause header.
51 Page 36, 6.2, Rule a I don't think you can prove this rule from outside the chip. If this is indeed the case, the rule should not be expressed this way. If you have to express it using AB1/2, then do it along the lines that the component "shall behave as if", not that "there must be".
52 Page 36-37, 6.2, Rules c/d, Recommendations e/f/g I suggest emphasizing the words current or voltage to highlight the differences between these. (E.g. underline)
53 **Page 37, 6.3, Rules There needs to be a rule which states that, "The ATAP pins shall be in the high impedance state when they are not instructed to be connected to the internal buses, VH, VL, or VG." Otherwise accurate measurements might be impossible, even if the impedance is documented.
54 Page 37, 6.3, Rule a This needs to be worded in terms of what is seen at the ATAP, not what is seen looking out from the chip internals.
55 Page 37, Rules c-f These rules do not identify when the action shall take place.
56 Page 38, Rule h How do you make the monitored value observable?
57 Page 38, Note to Rule h Incomprehensible!
58 **Page 38, Recommendation i Incomprehensible!
59 Page 39, first 2 lines I don't think that this is covered in the EXTEST specification
60 Page 40, 6.3, P0 bullet I don't understand what mandatory high-Z condition is being referred to. Change "It also provides the high-Z condition that is needed in EXTEST". Please explain.
61 Page 40, 6.3, Description For P0, the "high-Z condition that is needed in EXTEST" is different than for any other pin - it needs to be truly high impedance, as noted in my other comments. A note must be added referring to the proposed new rules for 6.3 and 9.4.
62 Page 41, Table 1 Missing in 3rd column 1st row. Change "andfunction" to "and function".
63 Page 41, Table 1 This includes "when" information absent from the rules
64 Page 43, Rule 6.4(b) The register bit name "CONTROL" was also used in the ABM (7.3.3b). A different name should (or must?) be used to avoid confusion.
65 Page 43, Rule 6.4(e) The phrase, "parallel loaded from the corresponding stages of the control register" doesn't appear to permit the latches to be connected to the output of the combinational logic, so as to prevent decoding glitches from reaching the switches. It should be modified to say, "parallel loaded from the corresponding stages of the control register and any necessary combinational logic, ... , such that serial shifting in the control register has no effect on the state of the switches."
66 Page 43, 6.4, Permission A permission is needed to allow driving the ATAP pins to VH or VL, for any instruction, to address the situation when they are not driven by any IC on a board.
67 Page 44, Figure 13 I understand that the Standard is using this boundary-scan cell implementation because it simplifies illustration, and see that the Standard explicitly states this earlier. However, I've seen too many designers start out this way "because it's in the standard". Can we insert an addition warning right here? Add "Note - correct boundary-scan register operation using the asynchronous boundary-scan cell implementation shown may require that the designer control the skew of the ClockDR signal."
68 Page 46, 6.5 Misspelling. Change "methodolgies" to "methodologies".
69 Page 47, 6.6.1 Is rule (a) (ii) too restrictive? Change "a set of four switches" to "a set of at least four switches".
70 Page 48, 6.6.1, Table 4 The text refers to "switches S5a - S10a replacing S5 - S10". The table refers to switch conditions 5n, 6n, 7n, 8n, 9n and 10n. These should be consistent. Change "switches S5a - S10a replacing S5 - S10" and "5n" (etc.) in table to "switches S5a - S10a replacing S5n - S10n" and "S5n" (etc.) in table.
71 Page 48, 6.6.1 Extra period. Change "supported.." to "supported.".
72 **Page 49, 6.6.2, Permission A new permission should be added to permit one or more 1149.4-compliant IC designs to be simply connected together on a single substrate (monolithic or MCM), and to appear as one IC. Without this, MCMs will get confusing. The needed Permission "(j) The entire TBIC may be replicated for any or all partitions, in which case only one bit shall be designated Co (all other former Co elements will be loaded with logic 0), and all Ca elements shall be designated Ca and loaded with the same value (logic 0 or 1)."
73 Page 51, 7.1, First para "Each analog function pin has associated with it an analog boundary module ..."
74 Page 51, 7.1, Description The first paragraph states, "and optionally allows signals to be applied to the core without having to pass through the function pins." It should be modified to say, "and optionally allows digital signals ...". An ABM has no way to route an analog signal to the core without going through a function pin.
75 Page 52, 7.2 I think that this can be deleted given the "based on 1149.1" rule earlier. The exception is permission d.
76 Page 52, 7.2 Make it clear that the statement will not be true of the revised standard. As is, this sound like "disregard IEEE Std 1149.1". Change "Notwithstanding the rules contained in IEEE Std. 1149.1" to "Notwithstanding the rules contained in the 1990 and 1993 versions of IEEE Std 1149.1".
77 Page 53, 7.2, Description A note should be appended to the last paragraph - "Note that an ABM does not make provision for driving the core only, or monitoring the core only, as is required for digital INTEST."
78 **Page 53, 7.3, Rule b I am not sure what this means. It implies that the ABM must be defined as an add-on, not as an integral part of the chip. Surely, the key is that the designer must achieve the required pin-to-pin performance and include the ABMs. This may be achieved through compensatory changes to the core design rather than by making the ABMs low impedance. This rule, as stated, is rather like expecting to find a statement in 1149.1 that insertion of boundary-scan cells shall not impact chip performance. (There isn't one!)
79 Page 54, 7.3, Rules e and f These rules need to include a quality statement. How must loss/distortion is acceptable? What kind of transformation is permitted (e.g., non-linear prohibited)?
80 Page 54, 7.3(h), NOTE 3 Please explain why the requirement holds for input pins. Change "NOTE 3 - The requirement to be able to drive VH and VL out of the pin holds for input as well as output pins." to "NOTE 3 - To facilitate network measurements, the requirement ...".
81 Page 54, Rule i Everything later is based on there being exactly one reference (e.g., tables that define ABM switching)
82 Page 60, 7.3.2, NOTE 1 and NOTE 2 In what sense will RUNBIST perform the same way as CLAMP and HIGHZ? Both CLAMP and HIGHZ must select the bypass register. RUNBIST can select anything. Change "RUNBIST will perform in the same way as" to "RUNBIST conditions device primaries in the same way as".
83 **Page 61, 7.3.3, Description The last sentence on the page states, "The number of Mode signals needed will depend on the range of instructions supported." There are no optional 1149.4 instructions, and both Mode1 and Mode 2 are always needed, hence the statement is wrong. It must be deleted.
84 **Page 63, 7.3.3 Standard makes an inaccurate assumption. It can't assume that control register stages are identified by names. Delete "because the individual stages of the control register are identified by name". Add documentation requirement to Chapter 10.
85 **Page 65, 8 This clause contains no rules and should be an informative annex.
86 Page 65, 8.1.1 Does Figure 1 illustrate the EXTEST instruction? Change "The EXTEST instruction can also be used ... as illustrated in Figure 1. In this case, all analog pins ... and capturing a binary equivalent of this voltage back into the driving module." By adding a Figure to illustrate this.
87 Page 66, Figure 23 Where is this Figure referred to in the text? Delete if not used.
88 **Page 66, 8.1.2, Permission It is often impractical to implement differential outputs that drive both pins to the same value. When both pins derive current from a single current source, then it is impossible to drive both outputs to full and equal logic values. This would prevent simple interconnect test from working. I think that neither Rule 7.3 nor 1149.1 explicitly prevent the following proposed permission, however, users would need to anticipate the permission. "(a) When one pin of a differential pin pair is driving VH or VL in test mode, the other pin may be disabled (high-Z state) if it has been programmed to drive the same state."
89 **Page 66, 8.1.2, Description Figure 23 is not referenced anywhere in the text. Also, I believe that it is not 1149.1 compliant as there is no observation of the single-ended output nor control of the single-ended input.
90 Page 68, 8.1.3, Description Figure 25 is not relevant to this standard, and should be deleted. It is fully addressed in 1149.1. The phrase, "for a differential input is to insert an optional scan cell, as described in IEEE Std. 1149.1," should be modified to say, "... to insert an optional boundary scan cell ...".
91 Page 70, 8.2, Description The sentence, "The principle of making an analog measurement without using an op-amp (or at least, without depending on the virtual earth principle) is illustrated in Figure 28 ..." should be re-phrased. The method shown in Figure 28 actually does require an op-amp and does use a virtual earth, as shown in detail in Figure 36. The sentence should read, "The principle of making an analog measurement without using any zero ohm connections or 'guarding' is illustrated in Figure 28 ..."
92 **Page 70, 8.2, Description The equation "Zv + Zs6 + Zsb2 >> Zd" is incorrect. It should be "Zv + Zab2 + Zpin >> Zd where Zv is the impedance to ground for the measurement system; Zab2 is the impedance to ground for AB2; Zpin is the unknown impedance to ground for the function pin." The value of Zs6+Zsb2 can be any value less than 10kohm (see Clause 9.4) and has no relationship to Zd for purposes of determining error.
93 **Page 72, 8.2, Description The equation , "Zv + Zs6 + Zsb2 >> Zsg is incorrect. It should be "Zv + Zab2 + Zf1 + Zf2 >> Zsg where Zv is the impedance to ground for the measurement system; Zab2 is the impedance to ground for AB2; Zf1 is the impedance to ground for the function pin F1; Zf2 is the impedance to ground for the function pin F2."
94 **Page 74, 8.3, Description The sentence, "With this particular network, we [have] six unknowns- the three impedances Z1, Z2, and Z3, the applied reference voltage VG, and the switch impedances associated with It and VG" is incorrect. It should be "With this particular network, we have five unknowns. They are the three impedances Z1, Z2, and Z3, the applied reference voltage VG, and the switch impedance associated with VG." The value of the other switch impedances associated with It does not enter any calculations, nor are we interested in them since they are in series with a current source. We cannot calculate the value of VG or the switch associated with it, unless VG is zero (ground).
95 Page 78, Rule 9.4(a) and (d) "(Vdd-Vss-0.2)/0.0002" should be re-written as "(Vdd - Vss - 200mV) / 200uA," to obtain a result in ohms and to clarify how the limit was derived.
96 **Page 79, Rule 9.4(g) Within this rule, reference must be made to Clause 9.5 which clarifies that the measurement error is after documented impedances and calibration are accounted for.
97 **Page 79, 9.4, Rules A new rule is needed which sets a limit on the input impedance (AC and DC) of the ATAP pins when they are not instructed to be connected to the internal buses, VH, VL, or VG.
98 Page 81, 9.5, Description The phrase, "... with a 1 kHz bandwidth anywhere between 100 Hz and 100 kHz", is incorrect. It should be, "... between 100 Hz and 10 kHz."
99 Page 82, 9.5.1, Description Figure 36 correctly shows one way to deliver a known current to a CUT. A simpler way should also be illustrated, which is the use of a voltage source with an output impedance equal to Rdc of Fig 36. A note should be added to the reference to these two figures saying, "For each CUT connected to AT1, the voltage across the source impedance, Rdc, will need to be measured to determine how much current is flowing through it and through the CUT."
100 **Page 84, 9.5.2, Description In Figure 37, the label for the X-axis, "AC signal (pk-pk volts about 1.5 V mean)" is incorrect. It must be "DC bias for 100 mV AC signal" or "DC bias for small signal AC"
101 Page 85, 10.1 How about ... "Components claiming conformance to this standard shall meet all the rules set out herein. NOTE - By virtue of rule 4.1a, this requires that the majority of rules of IEEE Std 1149.1 shall also be met."
102 Page 85, 10.2 Preface rules sub-clause with "In addition to ..." statement. Delete rule a. Delete rules c and d (restatement of 1149.1 rules without changes).
103 Page 86, 10.2(e) (v) Extra period. Change "... and the device pin that carries this current.." to "... and the device pin that carries this current.".
104 **Page 86, Rule 10.2(e) The following sub-clause must be added - "(vii) Any pin-specific impedances whose existence must be known so that less than 1% measurement error can be achieved, as specified by Rule 9.4(g). The impedance may be documented with only upper and/or lower limits, and measured via the ATAP." This rule is essential when, for example, a nominally 50 ohm pull-up exists on-chip with a resistance anywhere between 40 and 60 ohms - clearly 1% measurements of parallel resistances will be impossible.
105 Page 87, Rule 10.2(f) (v) The rule should be re-phrased to say, "Whether AT1 and/or AT2 are optionally capable of delivering a voltage and/or current to/from a function pin, as permitted by Recommendations 6.2(e)(f)(g) and Permission 6.2(h).
106 General Avoid the use of the term "chip". Use something formal like "component".
107 **General Add the following sentence before many of the "Rules" headings - "The rules below apply in addition to those of IEEE Std 1149.1." and delete those rules that are a restatement of those in 1149.1
108 General You need a rule somewhere that specifies that input pins shall be designed to tolerate (i.e. receive without destroying the chip) signals outside of normal operating levels (e.g., due to an on-board short).
109 **General My vote is negative for process reasons only. P1149.4/D18 depends on revisions to IEEE Std 1149.1. These revisions must be approved before P1149.4 can become a standard.

# Location Comment
1 Page 1, Forward Add the same legalese as is shown in Forward of 1149.1 - "IEEE Standards documents are adopted by ... standards documents."
2 Page 2, Paragraph 4 Delete extraneous period at end of paragraph.
3 Page 3, 3-column list "Cary Champlin" is redundant versus the list of WG members on Page 2.
4 Page 4, 5.3 Delete extraneous period.
5 Page 6, Paragraph 1 "organised" should be replaced with "organized" (spelling).
6 Page 8, Figure 2, caption Delete extraneous period.
7 Page 9, Figure 3, caption Delete extraneous period.
8 Page 9, Paragraph 3 Replace "digital Boundary-Scan Standard (IEEE Std 1149.1)" with "IEEE Std 1149.1 boundary scan".
9 Page 9, 1.2, Paragraph 2 The third objective is defined as testability within an IC. It is also mentioned, rightly so, that the specific implementation is ad-hoc and up to the designer. Even so, it would be useful to have an example of a hypothetical implementation of a "in-IC" test in section 8 "measurement methodology".
10 Page 9, 1.3 Background reading, is misplaced. It should be placed at the end of the standard as Annex A (informative). The title "Background reading" may be maintained, but IEEE's preference is the word "Bibliography."
11 Page 11 How can a previous version of a standard include or contain a later version. Does not 1149.1a-1993 include 1149.1-1990? When I ordered the boundary scan standard, I ordered 1149.1a-1993 which was the complete standard, not 1149.1-1990. Furthermore, is not 1149.1b-1994 a supplement to 1149.1a-1993 since it describes the BSDL features of items from 1149.1a-1993?
12 Page 12, 3, Definitions Should have three subclauses added (and the definitions would be renumbered, down to level 3). The title of Clause 3 should be "Definitions, abbreviations and acronyms, and voltage source symbols." Subclause 3.1 should be Definitions. "CUT" should be removed from the definitions and included in 3.2, Abbreviations and acronyms (which are unnumbered). Other abbreviations/acronyms to add to this subclause (which should not be removed from the existing definitions) include ABM, ATAP, DBM, TAP, and TBIC. The next subclause, 3.2, Voltage source symbols, should be left as it is in the draft but the terms should not be numbered. (These terms will not be carried into Std 100.)
13 Page 12 The multiple use of the terms 'chip', 'device', 'integrated circuit', 'IC', and 'component' to describe the integrated circuit that these test features are incorporated is confusing at best. In section 3.1, 3.2, and 3.3, we have the term "integrated circuit". In section 3.8, we have the term "chip". In section 3.15, we have the term "integrated circuits and discrete components". In section 3.20, we have the term "component pins". In section 3.22 we have the term "device pins". In section 3.23, we use the term "a switch is an electronic device". In rule 4.1(a) we have the term "chip". In rule 5.1(a) & (b), we have the term "component". In section 5.4, we have the term "component" yet in Figure 8 on the same page, we use the term "chip". In section 6.1, we have the term "integrated circuit". In section 8.1.1, we have both the terms "device" and "chip". In section 9.3, we have the terms "integrated circuit" and "IC". In rule 10.1(a), we use the term "component". None of these terms are defined or consistent! I recommend that a consistent set of definitions be added to Chapter 3 that define what we mean with respect to the integrate circuit that houses these test features.
14 Page 12, 3.3, Note 3 "... to perform the function of VG". If the positive and ground power supply voltages are used to define, respectively, VH and VL, these can be considered as reference quality voltages. This complements the sentence and makes it coherent with the last note on page 54 and rule © on page 78.
15 Page 12, 3.4 Period following "them" should be normal face, not bold.
16 Page 12, Figure 4, caption Delete extraneous period.
17 Page 13, 3.4 Period following "individually" should be normal face, not bold.
18 Page 13, 3.5 In the upcoming revision to 1149.1, the term "system logic" still exists, but is augmented by the terms "system mixed-signal circuitry" and "system circuitry" (which includes both logic and mixed-signal) - this note may need to be revised accordingly.
19 Page 13, 3.10 This definition suggests that digital pins may represent discrete (binary) values with either voltage or current, but further definitions (logic 0, 1) and usage suggest that only voltage representations are treated. this inconsistency should be corrected.
20 Page 15, Section 3.21 I don't believe the requirement to have the reference quality voltage stable over a defined current range is necessary. When a reference quality source such as VG is sourced through SG, the characteristics that make it reference quality are destroyed due to the resistance of the switch SG. The requirement for stability over time, however, is necessary.
21 Page 15, 3.23, sentence 2 replace "referred to" with "referred to as" (add "as").
22 Page 17, 3.29, NOTE The description "VG must be available at a chip pin....." appears only this page. Never appears in 7.3, etc. I think that If this is a rule, this should appear at least in 7.3.
23 Page 17, Section 3.29, Note Why must VG be available at a chip pin? If VG is externally sourced, the chip pin will be present. If VG is internally sourced, most designers would not want to waste a chip pin. If the user needs to observe VG, perhaps they could add a simplified ABM to "probe" VG.
24 Page 18, 4 The lines "Rule" and "Description" on page 18 should be numbered as subclauses 4.1.1 and 4.1.2. This holds true for Rules and Descriptions in subsequent subclauses. These should not be left as unnumbered lines of text. (In Clause 5, the line "Permission" should be treated in the same fashion, as should "Recommendation" in Clause 6.) In Clause 5, some subclauses will have to be renumbered as a result of this change.
25 Page 18, Note 1 Replace heading "Note - 1" with "Note 1 -".
26 Page 18, Section 4.1, Note 1 No reference to optional reset pin on TAP.
27 Page 18, Figure 5, caption Delete extraneous period.
28 Page 18, Figure 5 and 4.2 Figure shows a "test controller" and text refers to "TAP controller". If this is a TAP controller in the context of the 1149.1 standard, then it should be referenced as such in this standard.
29 Page 18, Rule 4.1(a) The phrase "apart from exceptions specifically noted herein" should be replaced with the phrasing used in rule 5.2(a).
30 Page 18, Rule 4.1(a) and Rule 5.2(a) What is the difference between these two rules? Is not rule 5.2(a) redundant with respect to rule 4.1(a)? Why is the significance in the use of two different terms "chip" and "component" in these two rules?
31 Page 21, 4.2.3, Rules When the TAP controller is in the Test-Logic-Reset state, shouldn't all VH, VL, and VG nodes be isolated from the analog pins, including ATAP?
32 Page 21, 4.3a Is "Each component shall contain an ATAP." I suggest "Each component claiming conformance to this standard shall contain an ATAP."
33 Page 22, Figure 7, caption Delete extraneous period.
34 Page 22, 4.3, Permission (also concerning Page 36, 6) Does this standard allow optional analog test busses, other than differential purpose (for example 3 analog test busses, 5 analog test busses)?
35 Page 22, Permission (d) The phrase "may contain up to two further analog pins" implies that one further pin is also allowed. Is this the intent? I didn't think so... If not, then delete "up to". Note in 6.5, it appears that AT1N and AT2N must be supplied as a pair.
36 Page 23, the paragraph immediately following (ii) At the end of the paragraph should be a period "." instead of a ",".
37 Page 26, 5.3, heading Delete extraneous period.
38 Page 26, 5.3.1, Rules When the BYPASS instruction is active, shouldn't all VH, VL, and VG nodes be isolated from the analog pins including ATAP?
39 Page 26, 5.3.2, Rules When the SAMPLE instruction is active, shouldn't all VH, VL, and VG nodes be isolated from the analog pins including ATAP?
40 Page 27, 5.3.3, Rules When the PRELOAD instruction is active, shouldn't all VH, VL, and VG nodes be isolated from the analog pins including ATAP?
41 Page 27 5.3.4, Rule (a), NOTE, The EXTEST instruction "NOTE - This implies that digital pins are isolated from the core". The 1149.1 does not require digital input pins be isolated from the core, only that the pin be monitored and the core be protected from random inputs causing damage to the core logic. Clock pins are provided a specific exception by having a monitor only cell. Recommend that the NOTE be change as follows - "NOTE - This implies that all outputs are isolated from the core and that all inputs are either isolated or observed by the DBM".
42 Page 27, 5.3.4 Rule c is missing. It should describe what will happen with analog function pins when the EXTEST instruction is active.
43 Page 28, Section 5.3.4, Description The statement "while the EXTEST instruction is selected, all function pins (analog and digital) are isolated from the core" is incorrect. 1149.1 allows "observe only" cell types on inputs which do not disconnect the digital function pin from the core. (see 1149.1a figure 10-17).
44 Page 28, 5.3.4, Description, middle of 1st paragraph In the sentence "The facilities incorporated into the boundary test structure allow ....", the term "boundary test structure" is not familiar. How about "boundary-scan test structure"?
45 Page 28, 5.3.4, Description, Paragraph 2 The EXTEST instruction Change "While the EXTEST instruction is selected, all function pins (analog and digital) are isolated from the core, so that the signals driven ..." to "While the EXTEST instruction is selected, all functional output pins (analog and digital) are isolated from the core and all functional input pins (analog and digital) are either isolated from the core or monitored by a DBM and the core logic is protected from damage due to random behavior of the inputs during EXTEST execution. This allows the signals driven ...".
46 Page 29, Figure 8, caption Delete extraneous period.
47 Page 30, 5.4.1, Rules The rules for the other instructions refer to the instruction being the "active" instruction, yet here INTEST is "selected".
48 Page 30, 5.4.1, Rule (a) "... all inputs to the digital part...". This implies that the clock input pin cannot be used. The 1149.1 provided the feature to allow single stepping during INTEST, which implies a free running clock could be used. Change to "... all inputs to the digital part are to be controlled by the boundary-scan register, except clocks which may be allowed to free run provided the part can be single stepped through the test sequence."
49 Page 31, Figure 9, caption Delete extraneous period.
50 Page 32, Figure 10, caption Delete extraneous period.
51 Page 33, When the IDCODE instruction is active, shouldn't all VH, VL, and VG nodes be isolated from the analog pins including ATAP?
52 Page 33, When the USERCODE instruction is active, shouldn't all VH, VL, and VG nodes be isolated from the analog pins including ATAP?
53 Page 33, Rule 5.4.3(a) This is the only optional instruction from the 1149.1 standard in this standard that is conditioned on existence. Why was the existence condition used on this RUNBIST instruction, and not on the other optional instructions (INTEST, IDCODE, CLAMP, HIGHZ) defined in this standard?
54 Page 33, 5.4.3 RUN BIST I would request the standard recommend a multiple bit signature. As described, it is possible (and within the spec) to have a single bit emitted as a success or failure. This is insufficient in my estimation. 1149.1 also suffers from this inadequacy.
55 Page 34 There should be a statement indicating that the ABM state does not change while the HIGHZ instruction is active. This means that if the instruction sequence EXTEST, HIGHZ, EXTEST were executed the state of the I/O state from the first EXTEST would be re-executed by the second EXTEST instruction. The same would be true for CLAMP.
56 Page 34, 5.4.4 The instruction only specifies the behavior of output pins. In many cases it is desired to also control the signals going to the analog core by means of the ABM's connected to input pins. It is suggested that while the CLAMP instruction is selected, all signals driving analog functions are defined by corresponding input ABM's.
57 Page 34, 5.4.4 and 5.4.5 What is the state of the TBIC for CLAMP and HIGHZ? Note later in Table 1 on page 41 that HIGHZ is mentioned for pattern P0. CLAMP is omitted. In Table 2 on page 42, CLAMP is mentioned. It seems we both sections need a rule b) that say "5.4.4 b) When the CLAMP function is selected, the state of the AT1/2 pins shall be defined by the data held in the TBIC control register (6.4).". "5.4.5 b) When the HIGHZ function is selected, the AT1/2 pins shall be in the high impedance state regardless of the data held in the TBIC control register (6.4).".
58 Page 36, Paragraph 1 The abbreviation "ATE" has no precedent which defines it or spells it out.
59 Page 36, Paragraph 2 Clause 6.4 is not described - should it be?
60 Page 37, Permission 6.2(h) This permission seems to allow permission to disregard rules 6.2© and 6.2(d). It appears that all of the conditions defined by rules 6.2© and 6.2(d) and recommendations 6.2(e-g) cover this permission. What is being permitted by 6.2(h) beyond these rules and recommendations? It should only be those items beyond the rules and recommendations that need permissions.
61 Page 37, 6.3 Rule © seem to prescribe that a current path through AB1 shall be possible to open from AT1 to AT2. However, rule (d) of section 6.2 states that it is only mandatory for AT2 to transmit voltage, and only from AB2. A similar inconsistency seem to exist between 6.3, rule (d) and 6.2, rule (d).
62 Page 37, 6.3, (c ) "AT1 shall be capable ... on to AB1 and through to AT2 without ...". Is anything missing between through and to in this sentence?
63 Page 38, 6.3 (i) Change from "Whenever an internal bus line ..." to "Whenever an internal analog test bus line ...". The rest of the standard uses the "internal analog test bus" phrasing.
64 Page 38, 6.3, Description The term "the analog test pins" In the 1st paragraph, "The analog test pins (AT1 and AT2) provide ...", and the term "ATAP pins" in the 2nd paragraph "At board level, ... to the ATAP pins of ..." point the same thing, should use same term.
65 Page 38, last line Subscript "L" overlays "V".
66 Page 39, Figure 11, caption Delete extraneous period.
67 Page 40, Figure 12, caption Delete extraneous period.
68 Page 40, Paragraph 5 Replace "P 1-3" with "P1-3" (delete extraneous space).
69 Page 40, 6.3, line 9 "a pair of drivers is controlled by three digital signals ...". I can see only one controlling digital signal in figure 12, signal C. Are these three C, D1 and D2? But D1 and D2 are identified later as inputs!
70 Page 40, Paragraph 2 "S5-S8" should be "S1-S4".
71 Page 41, Table 1 P1-P3 - There are three conditions. It is not clear the switch conditions in the PROBE, INTEST and EXTEST.P8-P9 - Not clear the difference between P8 and P9 without more digging into the document.
72 Page 41, 6.3, (j), Table 1 Is "Switch Conditions". Should be "Switch conditions". Is "Connections andfunction". Should be "Connections and function".
73 Page 42, Table 2, caption Delete extraneous period.
74 Page 42, 6.4(f) & 6.4(i) Are additional connection patterns and assignments allowed or not? Top line on page 42 states "Additional connection patterns could be provided to support optional instructions." Yet, the note 4 on page 42 does not allow a designer to add any codes to support the features associated with an optional/user-defined instruction. Rule 6.4(f) makes the assignments in Table 2 required. Yet, rule 6.4(i) allows additional switching patterns to support user-defined instructions. I am confused! Can this apparent confusion from a designer's perspective be cleared up? Do these rules also apply to additional ATAP pins and TBICs? My immediate concerns are two-fold - 1) Implementation of a single-end to single-end differential interface test and associated user-defined instructions as described in 8.1.3, and 2) Implementation of a differential interface parametric testing using the second set of ATAP pins.
75 Page 43, 6.4, Rule (f) For help of easier reading, show page of Table 1 and Table 2.
76 Page 45, Table 3, caption Delete extraneous period.
77 Page 45, NOTE below Table 3 Should be "Others" instead of "Other" to match what's in the table.
78 Page 45 The logic conditions for S1-S10. I wondered how this arrangement was developed. Without getting into a big analysis I wondered how difficult it would be to setup the switches. For example having switches S1 and S5 on, then off on the next test. Would a truth table help?
79 Page 46, 6.5, Rule (a) "... in accordance with Permission 4.3( c)," should read "... 4.3(d).".
80 Page 46, 6.5, line 21 Is "methodolgies arre". Should be "methodologies are".
81 Page 46, 6.6 I found the reference on the last line "as permitted by 6.2(i)" provided me with no additional information. I checked this reference to find it only stated it permitted this condition and it referred back to my previous reference.
82 Page 47, Section 6.6.1, Rule (b) Note The two additional switches implemented by recommendation 6.3(i) should be named (S9 and S10).
83 Page 47, 6.6.1 and 6.6.2 Use of the letter 'a' as a AB designation and as a valid word makes for some confusion when reading this clause. Can the use of single quotes around the letter 'a' be used when it refers to the AB designation? For consistency, the letter 'n' should be enclosed in single quotes, too.
84 Page 47, Figure 14, caption Delete extraneous period.
85 Page 48, Paragraph 1 Replace "switches S5a - S10a replacing S5 - S10" with "switches S5a - S10a replacing S5 - S10 and patterns P0a - P3a, P8a - P9a replacing P0 - 3, P8 - 9".
86 Page 48, Table 5, caption Delete extraneous period.
87 Page 48, Table 5 This table must either include Co in the "Code" listings or otherwise note that it is only valid when Co=0!! This is necessary because when the CONTROL stage of the base section has logic 1 value, only patterns P4-P7 should be provided.
88 Page 49, 6.6.2, Rule (f) Replace "CALIBRATE stage" with "CALIBRATE and CONTROL stages". This is necessary because when the CONTROL stage of the base section has logic 1 value, only patterns P4-P7 should be provided.
89 Page 50, Figure 15 Add bus wire connecting Co of base section to Control logic partition n. This is necessary because when the CONTROL stage of the base section has logic 1 value, only patterns P4-P7 should be provided.
90 Page 50 Logic equations. Same comments as page 45.
91 Page 50, equations Equations for "S" sub "5n" through "S" sub "8n" should include Co negated in the and term. This is necessary because when the CONTROL stage of the base section has logic 1 value, only patterns P4-P7 should be provided.
92 Page 52, Figure 16, caption Delete extraneous period.
93 Page 52, note 2 to (a) The provisions for the upcoming revision to 1149.1 do not require that all differential pins be regarded as analog - this note should be revised accordingly.
94 Page 52, Rule 7.2(a) & 7.2(d) Since when is a rule dependent on a permission? A permission should allow a designer/user to implement something beyond the rules. I recommend that the rule 7.2(a) be rewritten as "A DBM or an ABM shall be connected between each digital function pin and the core circuitry." Permission 7.2(d) can then be deleted.
95 Page 53, 7.2, Description PROBE is a new instruction for DBM, so the LSI designer should take care to the design of DBM or MODE signal from the TAP controller to satisfy the PROBE rules. I think some NOTE or description or MODE table should be added for the help of understanding in this section, though there is a rule in the 5.3.5 (b).
96 Page 53, 7.3 (c ), note 1 replace "Rule" with "rule" (lowercase).
97 Page 54, 7.3, (i) "NOTE- if the technology is such that either VH or VL is of reference ...". Should be "NOTE- if the technology is such that either or both VH or VL are of reference ...". It is not clear all over the draft if VH and VL may both be defined by the power supply voltages, respectively, VDD and VSS.
98 Page 55, Figure 17, caption Delete extraneous period.
99 Page 56, Figure 18, caption Delete extraneous period.
100 Page 56, Figure 19, caption Delete extraneous period.
101 Page 57, Figure 20, caption Delete extraneous period.
102 Page 58, Table 6, caption Delete extraneous period.
103 Page 58, Table 6 It would be useful to distinguish the patterns in this table versus the TBIC patterns of table 1 (perhaps by use of lowercase p?).
104 Page 60, Table 8, caption Delete extraneous period.
105 Page 60, Table 8 Delete extraneous periods following two instances of "CLAMP".
106 Page 61, Permissions (g) A NOTE should be added to caution the designer that the value captured could be executed without a scan sequence being performed by going from the CAPTURE-DR state, to the EXIT1-DR state, to the UPDATE-DR state. This may cause unwanted circuit action.
107 Page 62, Figure 21 The line for the ClockDR signal on the BUS1 capture flip-flop is too long.
108 Page 62, Figure 21 Very minor formatting. The Bus1 clock line has a little line overlap. Going for perfection.
109 Page 63, Table 9, caption Delete extraneous period.
110 Page 63, 7.3.3, (h), line 17 Suggestion to change input and output in "(i) on the rising edge of TCK ... load serially with input data from TDI" to "(i) on the rising edge of TCK ... load serially with internal data from TDI". From "(ii) on the rising edge of TCK ... loaded in parallel with output data, which" to "(ii) on the rising edge of TCK ... loaded in parallel with external data, which".
111 Page 65-74, 8 It is only recommendations of some well known methods of analog measurements. In my opinion, this section does not describe the IEEE P1149.4, but only gives suggestions of possible measurement methodology. So, I have the doubt as section 8 should be in the IEEE P1149.4.
112 Page 65, 8.1.1 This prose uses the word "track" for wire or net used elsewhere. I hope foreigners will be aware of the synonymous relation.
113 Page 66 "If this line is followed" should read "If this line of reasoning is followed"
114 Page 66, 8.1.2 Figure 23 is not referenced in the text!
115 Page 67, Section 8.1.3 The use of "simplified" ABMs which have the switches used for interconnect testing removed implies that rule 7.3(h) is violated. If simplified ABMs are allowed when not located on an analog function pin, a permission should be written. In addition, the standard does not specifically address the use of simplified ABMs for internal scan chains.
116 Page 67 "can be built in to the differential driver" should be "can be built into the differential driver"
117 Page 70 The word "earth" is used, synonymously with "GND" and "ground" elsewhere. Perhaps "ground" should be used exclusively.
118 Page 70, Section 8.2 "The measured voltage, VT, will be a good approximation to the voltage across the CUT if Zv + Zs6 + Zsb2 >> Zd". This is a necessary but not sufficient condition. The other condition is Zv >> Zs6 + Zsb2.
119 Page 70, 71, 80, 81 The symbol for Vt is that of a voltage source, no that of a measuring device. We should change the symbol.
120 Page 71, second sentence after the figure It begins with "... internal reference source". We are not clearly pointing out the requirements of the internal reference. The user must understand that this reference must conduct the current, It, back to the common source connection between the detector and the source. The characteristics of VG are that of a voltage source. It must be able to conduct the test current. It must be able to conduct the test current without an appreciable change in the voltage VG.
121 Page 72, Section 8.2 "Nearly all the current through the CUT will pass through switch SG to the reference source VG provided that Zv + Zs6 + Zsb2 >> Zg". This is true, but another condition is necessary to ensure that the voltage measurement system measures the voltage at F2 accurately. The other condition is Zv >> Zs6 + Zsb2.
122 Page 73, Section 8.3, Figure 31 Current IT1 not shown in figure. A figure for second experiment (IT2 applied to P3) would help clarify the measurement setups and results.
123 Page 73, Figure 31 I felt the arrows normally show current flow. Your label has a voltage. Also the currents IT1 and IT2 are not shown.
124 Page 73, Figure 31, caption Delete extraneous period.
125 Page 73, 8.3 Reference is made to a paper written by Parker et al concerning measuring complicated networks. Given the importance of the measurement technique, I would like to have seen a detailed description how the more complex networks are tested. Five years from now, the paper may be difficult to get or using the methods may have some legal difficulties.
126 Page 73, Paragraph 1 This paragraph references a rule 5.3.4© which does not exist. This rule belongs on page 27-28. Also, the paragraph seems to have some other logical inconsistencies (I don't see how the second requirement implies that VH or VL can be used if they are of reference quality - it would seem to be the first requirement that does so).
127 Page 74, line 1 Change "we six unknowns" to "there are six unknowns".
128 Page 74, First sentence Change "we six unknowns" to "we have six unknowns".
129 Page 74, 8.3, first line "With this particular network, we six unknowns ...". Something is missing in this sentence.
130 Page 74, Paragraph 1 Replace "we six" with "there are six" (grammar).
131 Page 74, first line Grammatical error, "we six".
132 Page 74 Minor formatting problem with the two symbols. The suffixes are too close together.
133 Page 75, Paragraph 3 Replace "minimised" with "minimized" (spelling).
134 Page 75, Paragraph 5 Replace "realised" with "realized" (spelling). Replace "tri-statable" with "3-state" (note, tri-state is TM by NSC).
135 Page 75, 9.2, line 24 "tri-statable voltage buffers ...". hen, page 76, line 5 "When tri-stateable voltage buffers ...". One of these tri-stat*** is mistaken.
136 Page 76, Figure 32, caption Delete extraneous period.
137 Page 76, Paragraph 2 Replace "tri-stateable" with "3-state" (note, tri-state is TM by NSC).
138 Page 77, Figure 33, caption Delete extraneous period.
139 Page 78, 9.4(a) and (d) Constants in equations should have units.
140 Page 78, (d) This seems to suggest that VG must be supplied directly from a (single) pin. Is this required? If so, it should be explicitly stated elsewhere. If not, then this rule must be reworded.
141 Page 78, e(ii) There is no units for 0.5 and 1.5
142 Page 79, 9.4(g) The measurement technique is poorly described. Is the 1K resistor on an analog function pin? Does the resistor have its other leg connected to the measurement system ground or to another analog function pin? Figures should be prepared for all test set-ups. Why is the bandwidth important when the measurement appears to be made at a single frequency? Even if one plans to use multiple frequencies to characterize the part, a bandwidth to the -3dB points will not achieve the response "flatness" to provide 1% accuracy. For 1% accuracy, bandwidth for the signal paths need to be defined to the 0.04 dB points.
143 Page 79, (g) Change "1000" to "1k" (consistency in annotation).
144 Page 79, (h) From the point of view of an IC manufacturer/vendor, this rule seems to be contrary to recommendation 7.3(j) which suggests that the VH and VL voltages should be supplied by the functional driver. I agree that if functional drivers cannot tolerate a short circuit for a reasonable and defined period, then they will not be very useful for boundary-scan interconnect test. However, many functional drivers must be able to source very high short-circuit currents and to require that they do so indefinitely without circuit failure is not appropriate. If this rule stands, then we will likely find that IC vendors will be highly reluctant to implement 7.3(j).
145 Page 79, Recommendation k Need phase limits and specs.
146 Page 79, 9.4, (k) Is "Any buffers used in the AT1/AB1 ... have a bandwith (3 dB) of ..." Should not it be "Any buffers used in the AT1/AB1 ... have a bandwidth (+/- 3 dB) of ..."?
147 Page 79, 9.4(k) The specification formats are being mixed. The path gains are described as percent while the bandwidth is in dB. The 10Hz to 10KHz specification is fine but the 3dB bandwidth of 0 - 100KHz doesn't make any sense. If one plans to use the part at 10Hz and 10KHz they will need to ensure that the 0.5% (0.04dB) band extends slightly further. One whole decade may be excessive. The 3dB points are locations that should be avoided if accuracy is desired. It would be better to describe the bandwidth out to the 0.04dB points.
148 Page 80, 9.4, line 6 Is "VSS >= Vapp >= VDD". Should not it be "VSS <= Vapp <= VDD"? Vapp is a DC voltage. According the standards should not it be VAPP? IAC is an AC current. According the standards should not it be Iac? In this case it should be (same page, line 8) Rsw1 = Vac/Iac.
149 Page 80, Figure 34, caption Delete extraneous period.
150 Page 81, Figure 35, caption Delete extraneous period.
151 Page 81, Paragraph 2 Replace "minimised" with "minimized" (spelling).
152 Page 82, and 83, bullet items Identify the figure referenced for each item or at the beginning of the section. This will allow the reader to more easily identify the paths being addressed.
153 Page 82, Section 9.5.1, AB1 impedance to ground The meaning of the text "AT1-S7-AB2-S6-AT2" is unclear. The sentence should be re-written to say "Switches S7 and S6 are closed to enable the path from AT1 to AT2 via AB2". A figure for this test set-up would be even better.
154 Page 82, Figure 36 Is the common node for Vdc and Vac connected to Vss? Why does Rdc have a switch?
155 Page 82, Figure 36, caption Delete extraneous period.
156 Page 83, bullet item 5 Replace "Figure 33(a)" with "Figure 33(b)" (?) figure 33(a) does not even have an "Rcom" element.
157 Page 85, 10 Missing documentation requirements for additional ATAP buses/pins that may be used for enhanced differential testing. If any additional ATAP buses, besides the required two, are implemented as part of the 1149.4 test features of an integrated circuit, then the number of buses, their pins, and their allocation to any internal analog test bus partitions and allocations to ABMs should be documented.
158 Page 86, 10.2 (e)(v) Eliminate one period "." at the end.
159 Page 86, 10.2 (e)(v) Similar to 9.4(d), this seems to suggest that VG must be supplied directly from a (single) pin. Is this required? If so, it should be explicitly stated elsewhere. If not, then this rule must be reworded.
160 Page 87, (f)(i) "boundary module" does not seem appropriate - should it read "control register"?
161 Page 87, (f)(iv) This seems to suggest that VH and VL must be determined directly from (separately single) pins. Is this required? I would think that VH and VL as well as Vth might be functions of supply pin voltages. If this is required, then it should be explicitly stated elsewhere. If not, then this rule must be reworded.
162 Page 87, (h) This section appears to identify areas of non-compliance to rules. Does this mean the part would not be accepted as compliant?
163 General First of all I thought the document was well written and well researched in its connections with 1149.1.
164 General General comments throughout the document. I much prefer the Description section starting before the Rules or Permissions sections. I found the section was easier to read from the Description point first.
165 General Prior to final submittal, we request that the figures be modified. Change the type font to 8-pt. Helvetica, and remove the boxes around all figures. Also, please remember at the time of submittal to supply a separate set of figures, clearly identified by figure number, in electronic form (EPS or TIFF).
166 General Please do not use acronyms as terms (e.g. CUT). Instead, create an acronyms clause and list al acronyms in it.
167 General Please make sure that all cross references point to valid terms. For example, in Note 2 in "switch", you have a cross reference to "conceptual switch, high-Z". Should it really be a cross reference to "conceptual switch", or does "conceptual switch, high-Z" need to be defined? Should be consistent with the use of words like "standardisation" vs. "standardization." We should choose between "s" and "z." Page 1, second line "standardisation" was used while on page 2, second line, "standardized" was used.
168 General There is no mention of a compliance pin. Definition of what the compliance pin implies or defines for P1149.4 should be made.
169 General There should be some documentation in the P1149.1 specification that provides some assurance that if a P1149.1 device was designed that the extra register bits added to the boundary scan register can be defined by existing BSDL without violating the standard. This would begin to reduce fears that if a design supported P1149.4 that the existing 1149.1 tools could be used to develop tests for the digital portion of the board for instructions such as EXTEST, PRELOAD, etc.

Access the Minutes of the August, 1998 Working Group Meeting.

To reach the Chair of the IEEE P1149.4 Working Group:

Adam Cron
c/o Lucent Technologies
Room 2A-156
1247 South Cedar Crest Blvd.
Allentown, PA 18103
fax: (610)712-2583