Suggestions for hardware implementation
Arnold Neumaier wrote:
> What if we propose implementing three different pipelines for
> floating-point operations in fixed, selectable rounding modes?
My first post to stds-1788, on Oct 4, was precisely on this Topic!
(Subject was: Pipelined Interval Arithmetic)
I pointed out that the IBM/Sony Cell processor (SIMD) could run the
left and right halves of the pipeline in different rounding modes,
and also had the ability to exchange halves, which is precisely
what is needed here (and is ALSO useful for complex arithmetic,
where the mixed-rounding capability would not be exploited).
Some x86 processors have the ability to switch rapidly between
two (cached) rounding modes, which may allow concurrent operations
with different roundings to be pipelined together. In general,
architectures that permit individual arithmetic operations to be
scheduled with different rounding modes attached should do quite
well, whether this is architected as rounding-control instruction
bits, prefixes (might be attractive in the x86 opcode space), or
separate rounding-control instructions that are nevertheless nicely
pipelined, should do quite well, probably better than dedicated
pipelines with fixed rounding modes.
In any case, David Hough put the priorities quite well: manufacturers
need MOTIVATION much more than implementation ideas!
I wonder whether the dependable-computing folks could help us out in
this regard: surely they have a significant need. But perhaps they
have developed their own methods already, exploiting existing hardware.
In any case, this strays a bit from the job of a standard -- even
though it is quite important to generate the necessary motivation.
Michel.
Sent: 2008-11-25 21:33:11 UTC