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Nelson, thank you for this very interesting mail.I attach two pictures. Both show a board that supplies hardware for an exact dot product (EDP). The first (done in 1993) is designed in full custom, the second (done in 2002) in FPGA technology. The first can be reproduced in large quantities very easily, the second not so easily. The chip on the first board computed an EDP in 1/4 of the time the Intel processor needed for computing a possibly wrong result in conventional floating-point arithmetic. The speed of the second board lies somewhere between the two.
The central chip on the second board can easily be designed at a mathematics insitute. But for the entire board some help is needed. The chip on the first board needs special design tools and expensive production facilities. But testing and reproduction is simpler in this case.
Both chips carry their own adder and multiplier. These would not be needed if the EDP would be integrated into the aithmetic unit of a floating-point processor.
Best regard Ulrich Am 20.01.2016 um 00:51 schrieb Nelson H. F. Beebe:
Recent discussions on this thread are debating the feasibility and advisability of implementing exact dot product and interval arithmetic in hardware. This morning, in an ACM Bulletin posting, I received notice that David Patterson is retiring after 40 years at UC/Berkeley. The posting had this intriguing comment from him:... Ever-more-powerful FPGAs (field programmable gate arrays) and astonishingly inexpensive custom chips mean anyone can afford to design hardware; the manufacturing cost at low volumes amazingly is just hundreds of dollars per custom design, not millions. ...That sentence links to this blog entry Agile Design for Hardware, Part II David Patterson and Borivoje Nikoli{\'c} http://www.eetimes.com/author.asp?section_id=36&doc_id=1327291 that provides cost estimates. Later, the story mentions Patterson's work on RISC-V, an open source CPU design already supported by GNU gcc and LLVM Clang compilers: RISC-V https://en.wikipedia.org/wiki/RISC-V Berkeley Hardware Floating-Point Units http://riscv.org/download.html#tab_hardfloat RISC-V Publications http://riscv.org/publications.html The Wikipedia article in its reference list contains links to the MIPS-V architecture manual. I've skimmed that manual, and found that MIPS-V has full support for 32-bit, 64-bit, and 128-bit binary floating-point arithmetic conforming to IEEE 754, including ADD, SUB, DIV, MUL, SQRT, and FMA, with all rounding modes, and both quiet and signaling NaN, with a short appendix on future directions for support of decimal formats. RISC-V has been designed to support 128-bit integer arithmetic, and a future 128-bit flat address space, and offers both scalar and vector instructions for arithmetic. Thus, with suitable collaboration, it MIGHT be feasible for list members promoting particular hardware features in support of interval arithmetic to actually obtain real silicon implementations, even if only in initially tiny production volumes. The open-source nature (BSD license) of the RISC-V CPU design might make widespread commercialization much more practical than in the past when primarily only vendors with multi-billion-dollar budgets could engage in CPU design and manufacture. ------------------------------------------------------------------------------- - Nelson H. F. Beebe Tel: +1 801 581 5254 - - University of Utah FAX: +1 801 581 4148 - - Department of Mathematics, 110 LCB Internet e-mail: beebe@xxxxxxxxxxxxx - - 155 S 1400 E RM 233 beebe@xxxxxxx beebe@xxxxxxxxxxxx - - Salt Lake City, UT 84112-0090, USA URL: http://www.math.utah.edu/~beebe/ - -------------------------------------------------------------------------------
-- Karlsruher Institut für Technologie (KIT) Institut für Angewandte und Numerische Mathematik D-76128 Karlsruhe, Germany Prof. Ulrich Kulisch Telefon: +49 721 608-42680 Fax: +49 721 608-46679 E-Mail: ulrich.kulisch@xxxxxxx www.kit.edu www.math.kit.edu/ianm2/~kulisch/ KIT - Universität des Landes Baden-Württemberg und nationales Großforschungszentrum in der Helmholtz-Gesellschaft
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