Re: discussion period begins, until Jan. 26: "natural interval extension": friendly amendment to M001.02 - NaNs
Recent discussions on this thread are debating the feasibility and
advisability of implementing exact dot product and interval arithmetic
in hardware.
This morning, in an ACM Bulletin posting, I received notice that David
Patterson is retiring after 40 years at UC/Berkeley. The posting had
this intriguing comment from him:
>> ...
>> Ever-more-powerful FPGAs (field programmable gate arrays) and
>> astonishingly inexpensive custom chips mean anyone can afford to
>> design hardware; the manufacturing cost at low volumes amazingly is
>> just hundreds of dollars per custom design, not millions.
>> ...
That sentence links to this blog entry
Agile Design for Hardware, Part II
David Patterson and Borivoje Nikoli{\'c}
http://www.eetimes.com/author.asp?section_id=36&doc_id=1327291
that provides cost estimates.
Later, the story mentions Patterson's work on RISC-V, an open source
CPU design already supported by GNU gcc and LLVM Clang compilers:
RISC-V
https://en.wikipedia.org/wiki/RISC-V
Berkeley Hardware Floating-Point Units
http://riscv.org/download.html#tab_hardfloat
RISC-V Publications
http://riscv.org/publications.html
The Wikipedia article in its reference list contains links to the
MIPS-V architecture manual. I've skimmed that manual, and found that
MIPS-V has full support for 32-bit, 64-bit, and 128-bit binary
floating-point arithmetic conforming to IEEE 754, including ADD, SUB,
DIV, MUL, SQRT, and FMA, with all rounding modes, and both quiet and
signaling NaN, with a short appendix on future directions for support
of decimal formats. RISC-V has been designed to support 128-bit
integer arithmetic, and a future 128-bit flat address space, and
offers both scalar and vector instructions for arithmetic.
Thus, with suitable collaboration, it MIGHT be feasible for list
members promoting particular hardware features in support of interval
arithmetic to actually obtain real silicon implementations, even if
only in initially tiny production volumes. The open-source nature
(BSD license) of the RISC-V CPU design might make widespread
commercialization much more practical than in the past when primarily
only vendors with multi-billion-dollar budgets could engage in CPU
design and manufacture.
-------------------------------------------------------------------------------
- Nelson H. F. Beebe Tel: +1 801 581 5254 -
- University of Utah FAX: +1 801 581 4148 -
- Department of Mathematics, 110 LCB Internet e-mail: beebe@xxxxxxxxxxxxx -
- 155 S 1400 E RM 233 beebe@xxxxxxx beebe@xxxxxxxxxxxx -
- Salt Lake City, UT 84112-0090, USA URL: http://www.math.utah.edu/~beebe/ -
-------------------------------------------------------------------------------