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[802.3_SPMD] Symbol aligner in 802.3 Clause 147 PCS

Hello,

We have a query regarding a possible false-lock scenario in PCS Receive state diagram (Figure 147-7).

In this figure, for multidrop use-case, there are 3 "out" transition from WAIT_SYNC state depending on the symbols received a.  to SYNCING state on reception of SYNC symbol b.  to BEACON1 state on reception of BEACOM symbol c.  to WAIT_SSD state on reception of SSD symbol.

However, the BEACON symbol & SSD symbol are very similar and prone to false-lock in an aligner when consecutive symbols are received 
2xBEACON symbols	=  01000 01000
2xSSD symbols                 =  00100 00100

For example, if 1st bit of actual BEACON reception (LSB "0") is lost/missed (which is practically possible with OA/TC14 3-pin PMD transceiver interface), then the subsequent pattern becomes equivalent to 2xSSD symbols. Hence the aligner in PMA can falsely lock to SSD instead of BEACON & thus the PCS state machine can falsely transition to WAIT_SSD instead of BEACON1 state & results in a loss of BEACON.  

My query : Considering that PCS TX always transmits at least 2 SYNC/COMMIT symbols before an SSD, should the PCS RX directly check for SSD symbol in WAIT_SYNC state. If we remove the transition of WAIT-SYNC to WAIT_SSD, then this false lock will not occur as it will first transition to SYNCING state on reception of SYNC symbol before moving to WAIT_SSD. 

Any comments on this resolution/ambiguity are appreciated.

Thanks,
Lokesh Kabra
 
 

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