RE: SONET/Ethernet clock tolerance
What I want to know is the pure technical comparison between your SONET
framer and the XGENIE ordered set insertion/removal circuits. Tim said
that SONET framer for your WAN-PHY proposal would be lighter than the
full-SONET framer, and hence I have tried to figure out how light it would be.
I would like to remind you that I am in the teleco company, and hence we
still need to buy 10GbE interface to our install-base SONET equipment.
They are usually specified to be SONET-compliant, and hence we need
+/-20ppm SONET-framed output; this would be SONET side of your ELTE.
Therefore we should buy another two interfaces; WAN-PHY at the router
and the Ethernet side of the ELTE. Here we have two choices; two SONET
framed WAN-PHYs or two XGENIE LAN-PHYs. Which is cheaper?
For this purpose, as a customer, I would like to know the technical
pros and cons in both candidates. It would be much appreciated if you
could show us your own offer, not the complaint to our estimations.
As for our evaluation results, you may misunderstand our chip. The chip
terminates the VC-4-16C (2.5Gb/s) alone, and hence it has a single
pointer processor, not the 16 pointer processors.
Therefore the whole 25% would be required in your chip. Note that most
part of this 25% seems to be related to buffer memory of several
hundreds of bytes for OH period accomodation. My guess is that the
30% reduction may available by cutting off the overhead access.
(I think this is much overestimated by our 180 bytes extra DCC.)
I won't go further in CLK distribution, since this depends on
partitioning and chip clk rate as Tim has pointed out.
As I said in the previous mail, I am not sure that the result on our
chip could be fair or not. Any additional information on your own
estimation would be appreciated.
At 9:39 AM -0500 00.4.12, David Martin wrote:
> You refer to an evaluation of power estimate savings if the pointer &
> OH functionality list from Tim's e-mail was not included in your
> example. Where are the results of that evaluation? What portion of
> the 55% for pointer & OH and the 45% clock tree power consumption
> is eliminated? Also, what portion of the I/O would be eliminated?
> Note further that you are referring to an OC-48 design, the savings
> will be even larger at OC-192 rate because several of the eliminated
> functions scale in complexity with line rate.
> At 7:33 PM +0900 00.4.12, Osamu ISHIDA wrote:
> > Tim,
> > Thank you for the precise information. I agree that we can cut off
> > most of the overhead access in your WAN-PHY with SONET framer. Thanks
> > to your illumination, I realized that I should estimate the consumption
> > power of each function block in our SDH VC-4-16c (2.5 Gb/s) Line
> > Terminating Chip.
> > Here are the rough estimation by my colleague Kenji Kawai of NTT who
> > designed the chip;
> > 25% Pointer Manipulation & Memory holding during overhead periods
> > 30% Full Overhead access
> > 45% Clock distribution in the chip
> > He excluded the consumption power for chip I/O and hence the above
> > 100% nearly equals 1.5 W. Note that we have implemented very heavy
> > extra DCC bytes (D13-D192), and hence the 30 % should be overestimated.
> > From this evaluation, at least in our design and process, we will have
> > relatively small impact of reduced overhead access on the total
> > cosumption power for the SONET line termination.
> > I am not sure that the result on our chip could be fair or not.
> > Any additional information on this matter would be appreciated.
> > Best Regards,
> > Osamu
> > At 3:20 PM -0400 00.4.11, Tim Armstrong wrote:
> > http://grouper.ieee.org/groups/802/3/10G_study/email/msg02260.html
> > -----Original Message-----
> > From: Osamu ISHIDA [SMTP:ishida@xxxxxxxxxxxxxxxxxxx]
> > http://grouper.ieee.org/groups/802/3/10G_study/email/msg02245.html
> > > At 4:56 PM -0500 00.4.10, Tim Armstrong wrote:
> > http://grouper.ieee.org/groups/802/3/10G_study/email/msg02241.html