| What is it about? |
| Program |
| Registration |
| Accommodation |
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This is
a 2-day Tutorial (Friday May 3rd and Saturday May 4th).
- After the introduction to the Boundary-Scan standard you will see relation between IEEE1149.1 and IEEE1149.4.
- In the second session you will learn about the architecture of IEEE1149.4 and its instructions. You will design basic IEEE1149.4 cells for your own products.
- In the third session you will understand the compliance rules and work on measurements using IEEE1149.4. You will also develop a test sequence and optimize it for an example circuit.
- In the fourth session you will learn how to use the remote sense capabilities of the IEEE1149.4 standard to develop measurements like LCR meters with an emphasis on accuracy, resolution and limitations. Automatic program generation and ABSDL will be examined.
Friday May 3rd, 2002 |
Saturday May 4th, 2002 |
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The first session of the 1149.4 Tutorial will bring you completely up to speed with the baseline functionality from which this Mixed-Signal Standard is derived: IEEE Standard 1149.1. The 1149.1 Standard addresses board- and system-level interconnect test requirements for digital signals. It provides the basic protocol and infrastructure on which IEEE 1149.4 is based. Session one provides an update and status on 1149.1 and 1149.4; the motivation behind providing support for these Standards in you designs; and complete introductions to the architectures and their applications. |
The third session will focus on using the test capabilities of an IC that is 1149.4 compliant. First, analog parameters of the 1149.4 circuitry that will be documented for each IC will be discussed, followed by a discussion on how to measure the bus parameters that must be accounted for in each subsequent measurement. Second, basic parametric test sequences will be described, such as measuring pin input/output impedances, pull-up resistances, local power rail voltages, and on-chip mixed-signal function performance. Examples will be drawn from an existing 1149.4 IC manufactured by National Semiconductor. Using the optional capabilities for 1149.4 will also be discussed, such as differential access and analog bus buffers. Attendees will be asked to write a test sequence for an example circuit, and various optimizations will then be considered. |
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The second session of the 1149.4 Tutorial will present the architecture of the mixed-signal test bus together with the instruction set and high-level design issues with regard to IC and board implementation of the standard. The fundamental blocks of the standard (the analog boundary module and the test bus interface circuit) will be discussed. Simple design exercises will be introduced and participants will be asked to design basic 1149.4 cells for their own products. This top-down view of the test bus links the overall introduction from the first session to the next two sessions on using the test bus facilities to test mixed-signal circuits and systems. |
The forth session examines the 1149.4 Mixed Signal Test Bus Standard as an architecture and protocol for applying stimulus to selected circuit nodes and measuring parameters. Measured parameters can be checked against a set of specifications to verify proper circuit operation -- otherwise known as functional testing. The standard can also be used determine if the circuit is composed of the intended components and whether the components are within specified tolerance limits -- known as structural testing. Structural testing assumes that a circuit will perform its mission when all components are within specified tolerance, that is, the circuit design is robust. This section will focus on the techniques for measuring single components and the accuracies achievable, verifying networks of components, and with the assumption of "few" failing parts, diagnosing what part has failed in a network of components. Structural testing has an additional advantage of being amenable to automatic program generation. This section will also examine methods to develop test programs automatically from the material list and circuit topology information. |
| A one-day schedule | |||||||||
| 08:30
10:00 |
Presentation | ||||||||
| 10:00
10:30 |
Break | ||||||||
| 10:30
11:00 |
Presentation | ||||||||
| Hands-on and Discussion | |||||||||
| 11:00
12:00 |
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| 12:00
01:00 |
Lunch | ||||||||
| 01:00
02:30 |
Presentation | ||||||||
| 02:30
03:00 |
Break | ||||||||
| 03:00
03:30 |
Presentation | ||||||||
| Hands-on and Discussion | |||||||||
| 03:30
04:30 |
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