IEEE Computer Society
Test Technology Technical Council (TTTC)

IEEE 3D-Test Working Group (3DT-WG)

Table of Contents


The semiconductor industry is preparing itself for three-dimensional stacked integrated circuits (3D-SICs), especially fueled by the advent of technologies based on Through-Silicon Vias (TSVs). TSVs are conducting nails which extend out of the backside of a thinned-down die and enable the vertical interconnection to another die. TSVs enable high-density, low-capacitance interconnects compared to traditional wire-bonds, and hence allow for many more interconnections between stacked dies, while operating at higher speeds and consuming less power. TSV-based 3D technologies enable the creation of a new generation of 'super chips' by opening up new architectural opportunities. 3D-SICs combine a smaller form factor and lower overall manufacturing cost with many other compelling benefits, and hence their technology is quickly gaining ground.

Like all micro-electronic products, 3D-SICs need to be tested for manufacturing defects, to filter out bad products and only deliver good products to the customer. A test access architecture transports test (data and control) signals for die and interconnect tests. In a post-bond stack situation, the external I/Os will typically be located on a single die, e.g., the bottom die, and hence the transportation of test stimuli and responses for a middle or top die has to propagate through all dies below it. This requires that the test access features integrated in each individual die are inter-operable and compatible with each other. This is even more true for an interconnect test, which by definition requires the two dies on either side of the interconnects to operate in concert with each other.

For 3D-SICs, three parties are involved: Die Maker(s), Stack Maker(s), and Stack User(s). All circuit features of the stack are included in the individual die designs. Design and integration of test access features needs to be done by the Die Maker(s), not only to serve their own (pre-stacking) test objectives, but also to serve test objectives of Stack Maker and Stack User. After stacking, test (control and data) signals need to be able to travel from the stack's external I/Os up and down through the stack. Hence, the test access features in the various dies of the stack need to function in a concerted and interoperable fashion. Different dies might have their own technologies, design set-up, and test and design-for-test approaches; the standard should not modify those. The standard defines test access features for a die that enable the transportation of test stimuli and responses both for testing THIS DIE and its inter-die connections, as well as for testing OTHER DIES in the stack and their inter-die connections.

This standard will bring the following benefits to its various users:


In January 2010, the IEEE 3D-Test Study Group was tasked to investigate whether or not there was a need and industrial support for one (or more) test and/or design-for-test standards in the domain of TSV-based 3D-SICs, and whether the timing was right to start developing these standards. This led to the formulation of a
Project Authorization Request (PAR) in November 2010, entitled "Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits". The PAR was approved by IEEE-SA's New Standards Committee (NesCom) on February 2, 2011, after which the Study Group transitioned in a Working Group, and the development on Project P1838 was started. On December 5, 2015, IEEE-SA's NesCom approved an extension request of the PAR until December 2018.

P1838 Project Authorization Request

PAR Title: Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits

Full PAR documents: Approved PAR, Extended PAR, Final PAR

Public Status Reports

Working Group Leadership and Officers

(e-mail addresses mangled to prevent spamming)

Working Group Membership

Membership of the 3DT-WG is open to interested professionals. Except for Working Group leadership positions, no membership (of IEEE, Computer Society, TTTC, TTSC, IEEE-SA, or otherwise) is required. The Working Group holds biweekly WebEx meetings on Thursdays, 8-9am US Pacific Time. Members are expected the attend and participate in these meetings. New members must express their interest to join to the 3DT-WG Chair and/or Vice-Chair.

The Working Group also keeps a "for-information only" mailing list, for individuals interested in the progress of the standard, but not able or willing to participate as an active member in our weekly meetings. Status updates on the progress of the Working Group are sent to this mailing list. Contact the 3DT-WG Chair and/or Vice-Chair if you want to be added to this mailing list.

Embedding in IEEE

IEEE, standardization activities reside under the IEEE Standards Association (IEEE-SA). We are the IEEE 3D-Test Working Group (3DT-WG), and within IEEE, we are sponsored by the Test Technology Standards Committee (TTSC), which belongs to the Test Technology Technical Council (TTTC) of IEEE Computer Society.

Membership of the 3DT-WG is open to interested professionals. Except for Working Group leadership positions, no membership (of IEEE, Computer Society, TTTC, TTSC, IEEE-SA, or otherwise) is required. At the time the draft P1838 standard will go to ballot, IEEE-SA membership will be required to be able to ballot on the standard (as per IEEE-SA rules).

3DT-WG adheres to the IEEE-SA Patent Policy. Among others, this implies that every meeting is started by showing the IEEE Patent Policy Slides, which include a Call for Potentially Essential Patents and see that for such cases, a Letter of Assurance (LOA) is submitted to IEEE. The current list of LOAs received by IEEE can be found here.


Erik Jan Marinissen - December 17, 2018